| Message ID | 20230328030631.3117129-19-gaosong@loongson.cn |
|---|---|
| State | New |
| Headers | show |
| Series | Add LoongArch LSX instructions | expand |
On 3/27/23 20:06, Song Gao wrote: > +static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) > +{ > + TCGv_vec t1; > + int64_t max = (1l << imm) - 1; This needed 1ull, but better to just use max = MAKE_64BIT_MASK(0, imm - 1); > + int64_t min = ~max; Extra space. > + t1 = tcg_temp_new_vec_matching(t); > + tcg_gen_dupi_vec(vece, t, min); > + tcg_gen_smax_vec(vece, t, a, t); Use tcg_constant_vec_matching(t, vece, min) instead of dupi. Three instances. > + tcg_gen_dupi_vec(vece, t1, max); > + tcg_gen_smin_vec(vece, t, t, t1); > +} > + > +static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, > + int64_t imm, uint32_t oprsz, uint32_t maxsz) > +{ > + static const TCGOpcode vecop_list[] = { > + INDEX_op_smax_vec, INDEX_op_smin_vec, 0 > + }; > + static const GVecGen2i op[4] = { > + { > + .fniv = gen_vsat_s, > + .fnoi = gen_helper_vsat_b, > + .opt_opc = vecop_list, > + .vece = MO_8 > + }, > + { > + .fniv = gen_vsat_s, > + .fnoi = gen_helper_vsat_h, > + .opt_opc = vecop_list, > + .vece = MO_16 > + }, > + { > + .fniv = gen_vsat_s, > + .fnoi = gen_helper_vsat_w, > + .opt_opc = vecop_list, > + .vece = MO_32 > + }, > + { > + .fniv = gen_vsat_s, > + .fnoi = gen_helper_vsat_d, > + .opt_opc = vecop_list, > + .vece = MO_64 > + }, > + }; > + > + tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); Better to expand imm to max here, rather than both inside gen_vsat_s and the runtime do_vsats_*. Likewise for the unsigned versions. r~
Hi, Richard 在 2023/4/1 下午1:03, Richard Henderson 写道: > On 3/27/23 20:06, Song Gao wrote: >> +static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, >> int64_t imm) >> +{ >> + TCGv_vec t1; >> + int64_t max = (1l << imm) - 1; > > This needed 1ull, but better to just use > > max = MAKE_64BIT_MASK(0, imm - 1); For the signed version use ll? I think use MAKE_64BIT_MASK(0, imm -1 ) for the signed version is not suitable. e.g imm is 1, imm is 1 1ll << imm -1 1 1ull << imm -1 1 MAKE_64BIT_MASK ffffffffffffffff vsat.w vr 22 vr25 0x1. input vr25: {0, 0} result vr22: {0, 0} if we use MAKE_64BIT_MASK , result is {ffffffffffffffff, ffffffffffffffff}. This is RISU test log: ...... imm is d 1ll << imm -1 1fff 1ull << imm -1 1fff MAKE_64BIT_MASK fff imm is 8 1ll << imm -1 ff 1ull << imm -1 ff MAKE_64BIT_MASK 7f imm is 7 1ll << imm -1 7f 1ull << imm -1 7f MAKE_64BIT_MASK 3f imm is 1d 1ll << imm -1 1fffffff 1ull << imm -1 1fffffff MAKE_64BIT_MASK fffffff imm is 29 1ll << imm -1 1ffffffffff 1ull << imm -1 1ffffffffff MAKE_64BIT_MASK ffffffffff imm is 6 1ll << imm -1 3f 1ull << imm -1 3f MAKE_64BIT_MASK 1f imm is 3 1ll << imm -1 7 1ull << imm -1 7 MAKE_64BIT_MASK 3 imm is 1 1ll << imm -1 1 1ull << imm -1 1 MAKE_64BIT_MASK ffffffffffffffff Mismatch reg after 63 checkpoints ...... mismatch detail (master : apprentice): f22 : 0000000000000000 vs ffffffffffffffff v22 : {0000000000000000, 0000000000000000} vs {ffffffffffffffff, ffffffffffffffff} Thanks. Song Gao.
On 4/3/23 05:55, gaosong wrote: > Hi, Richard > > 在 2023/4/1 下午1:03, Richard Henderson 写道: >> On 3/27/23 20:06, Song Gao wrote: >>> +static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) >>> +{ >>> + TCGv_vec t1; >>> + int64_t max = (1l << imm) - 1; >> >> This needed 1ull, but better to just use >> >> max = MAKE_64BIT_MASK(0, imm - 1); > For the signed version use ll? > I think use MAKE_64BIT_MASK(0, imm -1 ) for the signed version is not suitable. int64_t max = MAKE_64BIT_MASK(0, imm); int64_t min = ~max // or -1 - max
在 2023/4/4 上午4:13, Richard Henderson 写道: > On 4/3/23 05:55, gaosong wrote: >> Hi, Richard >> >> 在 2023/4/1 下午1:03, Richard Henderson 写道: >>> On 3/27/23 20:06, Song Gao wrote: >>>> +static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, >>>> int64_t imm) >>>> +{ >>>> + TCGv_vec t1; >>>> + int64_t max = (1l << imm) - 1; >>> >>> This needed 1ull, but better to just use >>> >>> max = MAKE_64BIT_MASK(0, imm - 1); >> For the signed version use ll? >> I think use MAKE_64BIT_MASK(0, imm -1 ) for the signed version is >> not suitable. > > int64_t max = MAKE_64BIT_MASK(0, imm); > int64_t min = ~max // or -1 - max > The same problem with imm = 0, MAKE_64BIT_MASK(0, 0) is always 0xffffffffffffffff. :-) Thanks. Song Gao
On 4/3/23 19:11, gaosong wrote: > > 在 2023/4/4 上午4:13, Richard Henderson 写道: >> On 4/3/23 05:55, gaosong wrote: >>> Hi, Richard >>> >>> 在 2023/4/1 下午1:03, Richard Henderson 写道: >>>> On 3/27/23 20:06, Song Gao wrote: >>>>> +static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) >>>>> +{ >>>>> + TCGv_vec t1; >>>>> + int64_t max = (1l << imm) - 1; >>>> >>>> This needed 1ull, but better to just use >>>> >>>> max = MAKE_64BIT_MASK(0, imm - 1); >>> For the signed version use ll? >>> I think use MAKE_64BIT_MASK(0, imm -1 ) for the signed version is not suitable. >> >> int64_t max = MAKE_64BIT_MASK(0, imm); >> int64_t min = ~max // or -1 - max >> > The same problem with imm = 0, > MAKE_64BIT_MASK(0, 0) is always 0xffffffffffffffff. :-) Huh. Well that's a bug. r~
Hi, Richard 在 2023/4/1 下午1:03, Richard Henderson 写道: > >> + tcg_gen_dupi_vec(vece, t1, max); >> + tcg_gen_smin_vec(vece, t, t, t1); >> +} >> + >> +static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, >> + int64_t imm, uint32_t oprsz, uint32_t maxsz) >> +{ >> + static const TCGOpcode vecop_list[] = { >> + INDEX_op_smax_vec, INDEX_op_smin_vec, 0 >> + }; >> + static const GVecGen2i op[4] = { >> + { >> + .fniv = gen_vsat_s, >> + .fnoi = gen_helper_vsat_b, >> + .opt_opc = vecop_list, >> + .vece = MO_8 >> + }, >> + { >> + .fniv = gen_vsat_s, >> + .fnoi = gen_helper_vsat_h, >> + .opt_opc = vecop_list, >> + .vece = MO_16 >> + }, >> + { >> + .fniv = gen_vsat_s, >> + .fnoi = gen_helper_vsat_w, >> + .opt_opc = vecop_list, >> + .vece = MO_32 >> + }, >> + { >> + .fniv = gen_vsat_s, >> + .fnoi = gen_helper_vsat_d, >> + .opt_opc = vecop_list, >> + .vece = MO_64 >> + }, >> + }; >> + >> + tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); > > Better to expand imm to max here, rather than both inside gen_vsat_s > and the runtime do_vsats_*. > > Likewise for the unsigned versions. I tried to expand imm to max here for the unsigned versions. { uint64_t max; ... static const GVecGen2i op[4] = { { //.fniv = gen_vsat_u, .fnoi = gen_helper_vsat_bu, .opt_opc = vecop_list, .vece = MO_8 }, { //.fniv = gen_vsat_u, .fnoi = gen_helper_vsat_hu, .opt_opc = vecop_list, .vece = MO_16 }, { //.fniv = gen_vsat_u, .fnoi = gen_helper_vsat_wu, .opt_opc = vecop_list, .vece = MO_32 }, { //.fniv = gen_vsat_u, .fnoi = gen_helper_vsat_du, .opt_opc = vecop_list, .vece = MO_64 }, }; max = (imm == 0x3f) ? UINT64_MAX : (1ull << (imm + 1)) - 1; tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, max, &op[vece]); } and I got a tcg_debug_assert(); Thread 1 "qemu-loongarch6" received signal SIGABRT, Aborted. 0x00007ffff60b337f in raise () from /lib64/libc.so.6 (gdb) bt #0 0x00007ffff60b337f in raise () from /lib64/libc.so.6 #1 0x00007ffff609ddb5 in abort () from /lib64/libc.so.6 #2 0x00007ffff609dc89 in __assert_fail_base.cold.0 () from /lib64/libc.so.6 #3 0x00007ffff60aba76 in __assert_fail () from /lib64/libc.so.6 #4 0x0000555555632fcf in simd_desc (oprsz=16, maxsz=16, data=134217727) at ../tcg/tcg-op-gvec.c:91 #5 0x000055555563312b in tcg_gen_gvec_2i_ool (dofs=768, aofs=432, c=0xb20, oprsz=16, maxsz=16, data=134217727, fn=0x5555555b5c00 <gen_helper_vsat_wu>) at ../tcg/tcg-op-gvec.c:139 #6 0x0000555555636085 in tcg_gen_gvec_2i (dofs=768, aofs=432, oprsz=16, maxsz=16, c=134217727, g=0x5555559c25b0 <op+112>) at ../tcg/tcg-op-gvec.c:1316 #7 0x00005555555e1ef5 in do_vsat_u (vece=2, vd_ofs=768, vj_ofs=432, imm=26, oprsz=16, maxsz=16) at ../target/loongarch/insn_trans/trans_lsx.c.inc:2828 #8 0x00005555555db25e in gvec_vv_i (ctx=0x7fffffffcc00, a=0x7fffffffcb00, mop=MO_32, func=0x5555555e1e73 <do_vsat_u>) at ../target/loongarch/insn_trans/trans_lsx.c.inc:121 #9 0x00005555555e1f80 in trans_vsat_wu (ctx=0x7fffffffcc00, a=0x7fffffffcb00) at ../target/loongarch/insn_trans/trans_lsx.c.inc:2833 #10 0x00005555555d2650 in decode (ctx=0x7fffffffcc00, insn=1932061023) at libqemu-loongarch64-linux-user.fa.p/decode-insns.c.inc:8967 #11 0x00005555555e8fca in loongarch_tr_translate_insn (dcbase=0x7fffffffcc00, cs=0x555555a4e5a0) at ../target/loongarch/translate.c:230 #12 0x000055555565e9ae in translator_loop (cpu=0x555555a4e5a0, tb=0x7fffe409f340 <code_gen_buffer+652051>, max_insns=0x7fffffffccfc, pc=274886330028, host_pc=0x40008086ac, ops=0x5555559c0960 <loongarch_tr_ops>, db=0x7fffffffcc00) at ../accel/tcg/translator.c:84 #13 0x00005555555e91d5 in gen_intermediate_code (cs=0x555555a4e5a0, tb=0x7fffe409f340 <code_gen_buffer+652051>, max_insns=0x7fffffffccfc, pc=274886330028, host_pc=0x40008086ac) at ../target/loongarch/translate.c:286 #14 0x000055555565d38b in setjmp_gen_code (env=0x555555a4e8f0, tb=0x7fffe409f340 <code_gen_buffer+652051>, pc=274886330028, host_pc=0x40008086ac, max_insns=0x7fffffffccfc, ti=0x7fffffffcd18) at ../accel/tcg/translate-all.c:285 #15 0x000055555565d64a in tb_gen_code (cpu=0x555555a4e5a0, pc=274886330028, cs_base=0, flags=0, cflags=0) at ../accel/tcg/translate-all.c:365 #16 0x00005555556556d6 in cpu_exec_loop (cpu=0x555555a4e5a0, sc=0x7fffffffce40) at ../accel/tcg/cpu-exec.c:977 #17 0x0000555555655859 in cpu_exec_setjmp (cpu=0x555555a4e5a0, sc=0x7fffffffce40) at ../accel/tcg/cpu-exec.c:1034 #18 0x00005555556558eb in cpu_exec (cpu=0x555555a4e5a0) at ../accel/tcg/cpu-exec.c:1060 #19 0x00005555555a75da in cpu_loop (env=0x555555a4e8f0) at ../linux-user/loongarch64/cpu_loop.c:22 #20 0x000055555567bc18 in main (argc=5, argv=0x7fffffffd708, envp=0x7fffffffd738) at ../linux-user/main.c:957 (gdb) frame 4 #4 0x0000555555632fcf in simd_desc (oprsz=16, maxsz=16, data=134217727) at ../tcg/tcg-op-gvec.c:91 91 tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS)); (gdb) p/x data $1 = 0x7ffffff (gdb) frame 7 #7 0x00005555555e1ef5 in do_vsat_u (vece=2, vd_ofs=768, vj_ofs=432, imm=26, oprsz=16, maxsz=16) at ../target/loongarch/insn_trans/trans_lsx.c.inc:2828 2828 tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, max, &op[vece]); (gdb) p/x max $2 = 0x7ffffff qemu-loongarch64: ../tcg/tcg-op-gvec.c:91: simd_desc: Assertion `data == sextract32(data, 0, (32 - ((0 + 8) + 2)))' failed. Could I drop this tcg_debug_assert()? Thanks. Song Gao
On 4/19/23 11:31, Song Gao wrote: > 在 2023/4/1 下午1:03, Richard Henderson 写道: >> Better to expand imm to max here, rather than both inside gen_vsat_s and the runtime >> do_vsats_*. >> >> Likewise for the unsigned versions. > > I tried to expand imm to max here for the unsigned versions. > > { > > uint64_t max; > > ... > > static const GVecGen2i op[4] = { > { > //.fniv = gen_vsat_u, > .fnoi = gen_helper_vsat_bu, > .opt_opc = vecop_list, > .vece = MO_8 > }, > { > //.fniv = gen_vsat_u, > .fnoi = gen_helper_vsat_hu, > .opt_opc = vecop_list, > .vece = MO_16 > }, > { > //.fniv = gen_vsat_u, > .fnoi = gen_helper_vsat_wu, > .opt_opc = vecop_list, > .vece = MO_32 > }, > { > //.fniv = gen_vsat_u, > .fnoi = gen_helper_vsat_du, > .opt_opc = vecop_list, > .vece = MO_64 > }, > }; > > max = (imm == 0x3f) ? UINT64_MAX : (1ull << (imm + 1)) - 1; > tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, max, &op[vece]); > > } > > > and I got a tcg_debug_assert(); > > > Thread 1 "qemu-loongarch6" received signal SIGABRT, Aborted. > 0x00007ffff60b337f in raise () from /lib64/libc.so.6 > (gdb) bt > #0 0x00007ffff60b337f in raise () from /lib64/libc.so.6 > #1 0x00007ffff609ddb5 in abort () from /lib64/libc.so.6 > #2 0x00007ffff609dc89 in __assert_fail_base.cold.0 () from /lib64/libc.so.6 > #3 0x00007ffff60aba76 in __assert_fail () from /lib64/libc.so.6 > #4 0x0000555555632fcf in simd_desc (oprsz=16, maxsz=16, data=134217727) at > ../tcg/tcg-op-gvec.c:91 You should use tcg_gen_gvec_2s, and pass tcg_constant_i64(max). r~
diff --git a/target/loongarch/disas.c b/target/loongarch/disas.c index 6e4f676a42..b04aefe3ed 100644 --- a/target/loongarch/disas.c +++ b/target/loongarch/disas.c @@ -1061,3 +1061,12 @@ INSN_LSX(vmod_bu, vvv) INSN_LSX(vmod_hu, vvv) INSN_LSX(vmod_wu, vvv) INSN_LSX(vmod_du, vvv) + +INSN_LSX(vsat_b, vv_i) +INSN_LSX(vsat_h, vv_i) +INSN_LSX(vsat_w, vv_i) +INSN_LSX(vsat_d, vv_i) +INSN_LSX(vsat_bu, vv_i) +INSN_LSX(vsat_hu, vv_i) +INSN_LSX(vsat_wu, vv_i) +INSN_LSX(vsat_du, vv_i) diff --git a/target/loongarch/helper.h b/target/loongarch/helper.h index e46f12cb65..6345b7ef9c 100644 --- a/target/loongarch/helper.h +++ b/target/loongarch/helper.h @@ -335,3 +335,12 @@ DEF_HELPER_4(vmod_bu, void, env, i32, i32, i32) DEF_HELPER_4(vmod_hu, void, env, i32, i32, i32) DEF_HELPER_4(vmod_wu, void, env, i32, i32, i32) DEF_HELPER_4(vmod_du, void, env, i32, i32, i32) + +DEF_HELPER_FLAGS_4(vsat_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_w, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_bu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_hu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_wu, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(vsat_du, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 46a18da6dd..7dfb3b33f6 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -2382,3 +2382,108 @@ TRANS(vmod_bu, gen_vvv, gen_helper_vmod_bu) TRANS(vmod_hu, gen_vvv, gen_helper_vmod_hu) TRANS(vmod_wu, gen_vvv, gen_helper_vmod_wu) TRANS(vmod_du, gen_vvv, gen_helper_vmod_du) + +static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) +{ + TCGv_vec t1; + int64_t max = (1l << imm) - 1; + int64_t min = ~max; + + t1 = tcg_temp_new_vec_matching(t); + tcg_gen_dupi_vec(vece, t, min); + tcg_gen_smax_vec(vece, t, a, t); + tcg_gen_dupi_vec(vece, t1, max); + tcg_gen_smin_vec(vece, t, t, t1); +} + +static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, + int64_t imm, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { + INDEX_op_smax_vec, INDEX_op_smin_vec, 0 + }; + static const GVecGen2i op[4] = { + { + .fniv = gen_vsat_s, + .fnoi = gen_helper_vsat_b, + .opt_opc = vecop_list, + .vece = MO_8 + }, + { + .fniv = gen_vsat_s, + .fnoi = gen_helper_vsat_h, + .opt_opc = vecop_list, + .vece = MO_16 + }, + { + .fniv = gen_vsat_s, + .fnoi = gen_helper_vsat_w, + .opt_opc = vecop_list, + .vece = MO_32 + }, + { + .fniv = gen_vsat_s, + .fnoi = gen_helper_vsat_d, + .opt_opc = vecop_list, + .vece = MO_64 + }, + }; + + tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); +} + +TRANS(vsat_b, gvec_vv_i, MO_8, do_vsat_s) +TRANS(vsat_h, gvec_vv_i, MO_16, do_vsat_s) +TRANS(vsat_w, gvec_vv_i, MO_32, do_vsat_s) +TRANS(vsat_d, gvec_vv_i, MO_64, do_vsat_s) + +static void gen_vsat_u(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) +{ + uint64_t max; + + max = (imm == 0x3f) ? UINT64_MAX : (1ul << (imm + 1)) - 1; + + tcg_gen_dupi_vec(vece, t, max); + tcg_gen_umin_vec(vece, t, a, t); +} + +static void do_vsat_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, + int64_t imm, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { + INDEX_op_umin_vec, 0 + }; + static const GVecGen2i op[4] = { + { + .fniv = gen_vsat_u, + .fnoi = gen_helper_vsat_bu, + .opt_opc = vecop_list, + .vece = MO_8 + }, + { + .fniv = gen_vsat_u, + .fnoi = gen_helper_vsat_hu, + .opt_opc = vecop_list, + .vece = MO_16 + }, + { + .fniv = gen_vsat_u, + .fnoi = gen_helper_vsat_wu, + .opt_opc = vecop_list, + .vece = MO_32 + }, + { + .fniv = gen_vsat_u, + .fnoi = gen_helper_vsat_du, + .opt_opc = vecop_list, + .vece = MO_64 + }, + }; + + tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); +} + +TRANS(vsat_bu, gvec_vv_i, MO_8, do_vsat_u) +TRANS(vsat_hu, gvec_vv_i, MO_16, do_vsat_u) +TRANS(vsat_wu, gvec_vv_i, MO_32, do_vsat_u) +TRANS(vsat_du, gvec_vv_i, MO_64, do_vsat_u) diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index 67d016edb7..3ed61b3d68 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -499,7 +499,10 @@ dbcl 0000 00000010 10101 ............... @i15 # @vv .... ........ ..... ..... vj:5 vd:5 &vv @vvv .... ........ ..... vk:5 vj:5 vd:5 &vvv +@vv_ui3 .... ........ ..... .. imm:3 vj:5 vd:5 &vv_i +@vv_ui4 .... ........ ..... . imm:4 vj:5 vd:5 &vv_i @vv_ui5 .... ........ ..... imm:5 vj:5 vd:5 &vv_i +@vv_ui6 .... ........ .... imm:6 vj:5 vd:5 &vv_i @vv_i5 .... ........ ..... imm:s5 vj:5 vd:5 &vv_i vadd_b 0111 00000000 10100 ..... ..... ..... @vvv @@ -757,3 +760,12 @@ vmod_bu 0111 00001110 01100 ..... ..... ..... @vvv vmod_hu 0111 00001110 01101 ..... ..... ..... @vvv vmod_wu 0111 00001110 01110 ..... ..... ..... @vvv vmod_du 0111 00001110 01111 ..... ..... ..... @vvv + +vsat_b 0111 00110010 01000 01 ... ..... ..... @vv_ui3 +vsat_h 0111 00110010 01000 1 .... ..... ..... @vv_ui4 +vsat_w 0111 00110010 01001 ..... ..... ..... @vv_ui5 +vsat_d 0111 00110010 0101 ...... ..... ..... @vv_ui6 +vsat_bu 0111 00110010 10000 01 ... ..... ..... @vv_ui3 +vsat_hu 0111 00110010 10000 1 .... ..... ..... @vv_ui4 +vsat_wu 0111 00110010 10001 ..... ..... ..... @vv_ui5 +vsat_du 0111 00110010 1001 ...... ..... ..... @vv_ui6 diff --git a/target/loongarch/lsx_helper.c b/target/loongarch/lsx_helper.c index 03a837fa74..15efc64e4e 100644 --- a/target/loongarch/lsx_helper.c +++ b/target/loongarch/lsx_helper.c @@ -763,3 +763,76 @@ DO_3OP(vmod_bu, 8, uint8_t, B, DO_REMU) DO_3OP(vmod_hu, 16, uint16_t, H, DO_REMU) DO_3OP(vmod_wu, 32, uint32_t, W, DO_REMU) DO_3OP(vmod_du, 64, uint64_t, D, DO_REMU) + +#define do_vsats(E, T) \ +static T do_vsats_ ## E(T s1, uint64_t imm) \ +{ \ + T mask,top; \ + \ + mask = (1l << imm) - 1; \ + top = s1 >> imm; \ + if (top > 0) { \ + return mask; \ + } else if (top < -1) { \ + return ~mask; \ + } else { \ + return s1; \ + } \ +} + +do_vsats(B, int8_t) +do_vsats(H, int16_t) +do_vsats(W, int32_t) +do_vsats(D, int64_t) + +#define VSAT_S(NAME, BIT, E) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t v) \ +{ \ + int i; \ + VReg *Vd = (VReg *)vd; \ + VReg *Vj = (VReg *)vj; \ + \ + for (i = 0; i < LSX_LEN/BIT; i++) { \ + Vd->E(i) = do_vsats_ ## E(Vj->E(i), imm); \ + } \ +} + +VSAT_S(vsat_b, 8, B) +VSAT_S(vsat_h, 16, H) +VSAT_S(vsat_w, 32, W) +VSAT_S(vsat_d, 64, D) + +#define do_vsatu(E, T) \ +static T do_vsatu_ ## E(T s1, uint64_t imm) \ +{ \ + uint64_t max; \ + \ + max = (imm == 0x3f) ? UINT64_MAX : (1ul << (imm + 1)) - 1; \ + if (s1 >(T)max) { \ + return (T)max; \ + } else { \ + return s1; \ + } \ +} + +do_vsatu(B, uint8_t) +do_vsatu(H, uint16_t) +do_vsatu(W, uint32_t) +do_vsatu(D, uint64_t) + +#define VSAT_U(NAME, BIT, T, E) \ +void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t v) \ +{ \ + int i; \ + VReg *Vd = (VReg *)vd; \ + VReg *Vj = (VReg *)vj; \ + \ + for (i = 0; i < LSX_LEN/BIT; i++) { \ + Vd->E(i) = do_vsatu_ ## E((T)Vj->E(i), imm); \ + } \ +} + +VSAT_U(vsat_bu, 8, uint8_t, B) +VSAT_U(vsat_hu, 16, uint16_t, H) +VSAT_U(vsat_wu, 32, uint32_t, W) +VSAT_U(vsat_du, 64, uint64_t, D)
This patch includes: - VSAT.{B/H/W/D}[U]. Signed-off-by: Song Gao <gaosong@loongson.cn> --- target/loongarch/disas.c | 9 ++ target/loongarch/helper.h | 9 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 105 ++++++++++++++++++++ target/loongarch/insns.decode | 12 +++ target/loongarch/lsx_helper.c | 73 ++++++++++++++ 5 files changed, 208 insertions(+)