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[02/23] target/arm: Correct syndrome for ATS12NSO* at Secure EL1

Message ID 20230127175507.2895013-3-peter.maydell@linaro.org
State New
Headers show
Series target/arm: Implement FEAT_FGT fine-grained traps | expand

Commit Message

Peter Maydell Jan. 27, 2023, 5:54 p.m. UTC
The AArch32 ATS12NSO* address translation operations are supposed to
trap to either EL2 or EL3 if they're executed at Secure EL1 (which
can only happen if EL3 is AArch64).  We implement this, but we got
the syndrome value wrong: like other traps to EL2 or EL3 on an
AArch32 cpreg access, they should report the 0x3 syndrome, not the
0x0 'uncategorized' syndrome.  This is clear in the access pseudocode
for these instructions.

Fix the syndrome value for these operations by correcting the
returned value from the ats_access() function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Richard Henderson Jan. 28, 2023, 1:04 a.m. UTC | #1
On 1/27/23 07:54, Peter Maydell wrote:
> The AArch32 ATS12NSO* address translation operations are supposed to
> trap to either EL2 or EL3 if they're executed at Secure EL1 (which
> can only happen if EL3 is AArch64).  We implement this, but we got
> the syndrome value wrong: like other traps to EL2 or EL3 on an
> AArch32 cpreg access, they should report the 0x3 syndrome, not the
> 0x0 'uncategorized' syndrome.  This is clear in the access pseudocode
> for these instructions.
> 
> Fix the syndrome value for these operations by correcting the
> returned value from the ats_access() function.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/helper.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

> 
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index ccb7d1e1712..6f6772d8e04 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -3284,9 +3284,9 @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
>           if (arm_current_el(env) == 1) {
>               if (arm_is_secure_below_el3(env)) {
>                   if (env->cp15.scr_el3 & SCR_EEL2) {
> -                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
> +                    return CP_ACCESS_TRAP_EL2;
>                   }
> -                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
> +                return CP_ACCESS_TRAP_EL3;
>               }
>               return CP_ACCESS_TRAP_UNCATEGORIZED;
>           }
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Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index ccb7d1e1712..6f6772d8e04 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3284,9 +3284,9 @@  static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
         if (arm_current_el(env) == 1) {
             if (arm_is_secure_below_el3(env)) {
                 if (env->cp15.scr_el3 & SCR_EEL2) {
-                    return CP_ACCESS_TRAP_UNCATEGORIZED_EL2;
+                    return CP_ACCESS_TRAP_EL2;
                 }
-                return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
+                return CP_ACCESS_TRAP_EL3;
             }
             return CP_ACCESS_TRAP_UNCATEGORIZED;
         }