| Message ID | 20230120073913.1028407-1-alistair.francis@opensource.wdc.com |
|---|---|
| State | New |
| Headers | show |
On Fri, 20 Jan 2023 at 07:47, Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.francis@wdc.com> > > The following changes since commit 239b8b0699a222fd21da1c5fdeba0a2456085a47: > > Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-01-19 15:05:29 +0000) > > are available in the Git repository at: > > https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230120 > > for you to fetch changes up to b748352c555b42d497fe8ee00ee2e44eb8627660: > > hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() (2023-01-20 10:14:14 +1000) > > ---------------------------------------------------------------- > Second RISC-V PR for QEMU 8.0 > > * riscv_htif: Support console output via proxy syscall > * Cleanup firmware and device tree loading > * Fix elen check when using vector extensions > * add RISC-V OpenSBI boot test > * Ensure we always follow MISA parsing > * Fix up masking of vsip/vsie accesses > * Trap on writes to stimecmp from VS when hvictl.VTI=1 > * Introduce helper_set_rounding_mode_chkfrm > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM
From: Alistair Francis <alistair.francis@wdc.com> The following changes since commit 239b8b0699a222fd21da1c5fdeba0a2456085a47: Merge tag 'trivial-branch-for-8.0-pull-request' of https://gitlab.com/laurent_vivier/qemu into staging (2023-01-19 15:05:29 +0000) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20230120 for you to fetch changes up to b748352c555b42d497fe8ee00ee2e44eb8627660: hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() (2023-01-20 10:14:14 +1000) ---------------------------------------------------------------- Second RISC-V PR for QEMU 8.0 * riscv_htif: Support console output via proxy syscall * Cleanup firmware and device tree loading * Fix elen check when using vector extensions * add RISC-V OpenSBI boot test * Ensure we always follow MISA parsing * Fix up masking of vsip/vsie accesses * Trap on writes to stimecmp from VS when hvictl.VTI=1 * Introduce helper_set_rounding_mode_chkfrm ---------------------------------------------------------------- Andrew Bresticker (2): target/riscv: Fix up masking of vsip/vsie accesses target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 Bin Meng (11): hw/char: riscv_htif: Avoid using magic numbers hw/char: riscv_htif: Drop {to, from}host_size in HTIFState hw/char: riscv_htif: Drop useless assignment of memory region hw/char: riscv_htif: Use conventional 's' for HTIFState hw/char: riscv_htif: Move registers from CPUArchState to HTIFState hw/char: riscv_htif: Remove forward declarations for non-existent variables hw/char: riscv_htif: Support console output via proxy syscall hw/riscv: spike: Remove the out-of-date comments hw/riscv/boot.c: Introduce riscv_find_firmware() hw/riscv: spike: Decouple create_fdt() dependency to ELF loading target/riscv: Use TARGET_FMT_lx for env->mhartid Daniel Henrique Barboza (20): hw/riscv/boot.c: make riscv_find_firmware() static hw/riscv/boot.c: introduce riscv_default_firmware_name() tests/avocado: add RISC-V OpenSBI boot test hw/riscv/spike: use 'fdt' from MachineState hw/riscv/sifive_u: use 'fdt' from MachineState hw/riscv/boot.c: exit early if filename is NULL in load functions hw/riscv/spike.c: load initrd right after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv/boot.c: use MachineState in riscv_load_kernel() target/riscv/cpu: set cpu->cfg in register_cpu_props() target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() hw/riscv/spike.c: simplify create_fdt() hw/riscv/virt.c: simplify create_fdt() hw/riscv/sifive_u.c: simplify create_fdt() hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() Dongxue Zhang (1): target/riscv/cpu.c: Fix elen check Richard Henderson (3): tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst target/riscv: Introduce helper_set_rounding_mode_chkfrm target/riscv: Remove helper_set_rod_rounding_mode include/hw/char/riscv_htif.h | 19 +- include/hw/riscv/boot.h | 9 +- include/hw/riscv/numa.h | 10 +- include/hw/riscv/sifive_u.h | 3 - include/hw/riscv/spike.h | 2 - target/riscv/cpu.h | 8 +- target/riscv/helper.h | 2 +- hw/char/riscv_htif.c | 172 +++++++----- hw/riscv/boot.c | 105 +++++--- hw/riscv/microchip_pfsoc.c | 12 +- hw/riscv/numa.c | 14 +- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 3 +- hw/riscv/sifive_u.c | 53 ++-- hw/riscv/spike.c | 108 ++++---- hw/riscv/virt.c | 86 +++--- target/riscv/cpu.c | 445 ++++++++++++++++++-------------- target/riscv/csr.c | 41 ++- target/riscv/fpu_helper.c | 36 ++- target/riscv/machine.c | 6 +- target/riscv/translate.c | 21 +- target/riscv/insn_trans/trans_rvv.c.inc | 24 +- tcg/riscv/tcg-target.c.inc | 2 +- tests/avocado/riscv_opensbi.py | 65 +++++ 24 files changed, 713 insertions(+), 536 deletions(-) create mode 100644 tests/avocado/riscv_opensbi.py