Message ID | 20221111182535.64844-13-alex.bennee@linaro.org |
---|---|
State | New |
Headers | show
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Fri, 11 Nov 2022 10:25:39 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D05821FFC3; Fri, 11 Nov 2022 18:25:36 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org> To: qemu-devel@nongnu.org Cc: f4bug@amsat.org, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Bin Meng <bin.meng@windriver.com>, qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs) Subject: [PATCH v5 12/20] target/riscv: initialise MemTxAttrs for CPU access Date: Fri, 11 Nov 2022 18:25:27 +0000 Message-Id: <20221111182535.64844-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221111182535.64844-1-alex.bennee@linaro.org> References: <20221111182535.64844-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; 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Series |
use MemTxAttrs to avoid current_cpu in hw/
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expand
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diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 278d163803..e661f9e68a 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -761,7 +761,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, * correct, but the value visible to the exception handler * (riscv_cpu_do_interrupt) is correct */ MemTxResult res; - MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; + MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env)); int mode = mmu_idx & TB_FLAGS_PRIV_MMU_MASK; bool use_background = false; hwaddr ppn;
get_physical_address works in the CPU context. Use the new MEMTXATTRS_CPU constructor to ensure the correct CPU id is filled in should it ever be needed by any devices later. Currently the tlb_fill function isn't using the set with attributes function so IO accesses from the softmmu slow-path will not be tagged as coming from the CPU. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)