diff mbox series

[v5,11/20] target/sparc: initialise MemTxAttrs for CPU access

Message ID 20221111182535.64844-12-alex.bennee@linaro.org
State New
Headers show
Series use MemTxAttrs to avoid current_cpu in hw/ | expand

Commit Message

Alex Bennée Nov. 11, 2022, 6:25 p.m. UTC 
Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
with CPU based access. Use the new MEMTXATTRS_CPU constructor to
ensure the correct CPU id is filled in should it ever be needed by any
devices later.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
 target/sparc/mmu_helper.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Mark Cave-Ayland Nov. 12, 2022, 1:02 a.m. UTC | #1 
On 11/11/2022 18:25, Alex Bennée wrote:

> Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
> with CPU based access. Use the new MEMTXATTRS_CPU constructor to
> ensure the correct CPU id is filled in should it ever be needed by any
> devices later.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>   target/sparc/mmu_helper.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
> index 919448a494..eeb52b5ee6 100644
> --- a/target/sparc/mmu_helper.c
> +++ b/target/sparc/mmu_helper.c
> @@ -212,7 +212,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>       target_ulong vaddr;
>       target_ulong page_size;
>       int error_code = 0, prot, access_index;
> -    MemTxAttrs attrs = {};
> +    MemTxAttrs attrs = MEMTXATTRS_CPU(cs);
>   
>       /*
>        * TODO: If we ever need tlb_vaddr_to_host for this target,
> @@ -771,7 +771,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
>       target_ulong vaddr;
>       hwaddr paddr;
>       target_ulong page_size;
> -    MemTxAttrs attrs = {};
> +    MemTxAttrs attrs = MEMTXATTRS_CPU(cs);
>       int error_code = 0, prot, access_index;
>   
>       address &= TARGET_PAGE_MASK;
> @@ -890,7 +890,7 @@ static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
>   {
>       target_ulong page_size;
>       int prot, access_index;
> -    MemTxAttrs attrs = {};
> +    MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env));
>   
>       return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
>                                   rw, mmu_idx, &page_size);

Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>


ATB,

Mark.
Richard Henderson Nov. 12, 2022, 5:38 a.m. UTC | #2 
On 11/12/22 04:25, Alex Bennée wrote:
> Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
> with CPU based access. Use the new MEMTXATTRS_CPU constructor to
> ensure the correct CPU id is filled in should it ever be needed by any
> devices later.
> 
> Signed-off-by: Alex Bennée<alex.bennee@linaro.org>
> ---
>   target/sparc/mmu_helper.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
Philippe Mathieu-Daudé Nov. 13, 2022, 7:45 p.m. UTC | #3 
On 11/11/22 19:25, Alex Bennée wrote:
> Both of the TLB fill functions and the cpu_sparc_get_phys_page deal
> with CPU based access. Use the new MEMTXATTRS_CPU constructor to
> ensure the correct CPU id is filled in should it ever be needed by any
> devices later.
> 
> Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
> ---
>   target/sparc/mmu_helper.c | 6 +++---
>   1 file changed, 3 insertions(+), 3 deletions(-)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
diff mbox series

Patch

diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c
index 919448a494..eeb52b5ee6 100644
--- a/target/sparc/mmu_helper.c
+++ b/target/sparc/mmu_helper.c
@@ -212,7 +212,7 @@  bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     target_ulong vaddr;
     target_ulong page_size;
     int error_code = 0, prot, access_index;
-    MemTxAttrs attrs = {};
+    MemTxAttrs attrs = MEMTXATTRS_CPU(cs);
 
     /*
      * TODO: If we ever need tlb_vaddr_to_host for this target,
@@ -771,7 +771,7 @@  bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
     target_ulong vaddr;
     hwaddr paddr;
     target_ulong page_size;
-    MemTxAttrs attrs = {};
+    MemTxAttrs attrs = MEMTXATTRS_CPU(cs);
     int error_code = 0, prot, access_index;
 
     address &= TARGET_PAGE_MASK;
@@ -890,7 +890,7 @@  static int cpu_sparc_get_phys_page(CPUSPARCState *env, hwaddr *phys,
 {
     target_ulong page_size;
     int prot, access_index;
-    MemTxAttrs attrs = {};
+    MemTxAttrs attrs = MEMTXATTRS_CPU(env_cpu(env));
 
     return get_physical_address(env, phys, &prot, &access_index, &attrs, addr,
                                 rw, mmu_idx, &page_size);