| Message ID | 20220428132717.84190-1-alex.zuepke@tum.de |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: read access to performance counters from EL0 | expand |
Hi, wanted to ping again on this issue before it gets lost. Am 28.04.22 um 15:27 schrieb Alex Zuepke: > The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access > to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, > we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. I configure PMUSERENR_EL0.ER for read access to the performance counters in user space, but it only works when I use the indexed access via the PMXEVCNTR_EL0 register, and not the direct access via the PMEVCNTR<n>_EL0 registers. Real Cortex-A53: PMXEVCNTR_EL0 read access in user space OK PMEVCNTR<n>_EL0 read access works QEMU: PMXEVCNTR_EL0 read access works PMEVCNTR<n>_EL0 exception The patch changes the access function for 32-bit mode PMEVCNTR<n> and 64-bit mode PMEVCNTR<n>_EL0 registers to the one from the "X" variant. Best regards Alex > Signed-off-by: Alex Zuepke <alex.zuepke@tum.de> > --- > target/arm/helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 63397bbac1..eb42b22766 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -6679,10 +6679,10 @@ static void define_pmu_regs(ARMCPU *cpu) > .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, > .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, > .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, > - .accessfn = pmreg_access }, > + .accessfn = pmreg_access_xevcntr }, > { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), > - .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, > + .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, > .type = ARM_CP_IO, > .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, > .raw_readfn = pmevcntr_rawread,
On Wed, 4 May 2022 at 09:20, Alex Zuepke <alex.zuepke@tum.de> wrote: > > Hi, > > wanted to ping again on this issue before it gets lost. Thanks for the ping; this is on my to-review queue and I'll probably get to it later this week. -- PMM
On 4/28/22 06:27, Alex Zuepke wrote: > The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access > to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, > we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. > > Signed-off-by: Alex Zuepke<alex.zuepke@tum.de> > --- > target/arm/helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Thu, 28 Apr 2022 at 14:28, Alex Zuepke <alex.zuepke@tum.de> wrote: > > The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access > to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, > we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. > > Signed-off-by: Alex Zuepke <alex.zuepke@tum.de> > --- > target/arm/helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Applied to target-arm.next, thanks. -- PMM
diff --git a/target/arm/helper.c b/target/arm/helper.c index 63397bbac1..eb42b22766 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6679,10 +6679,10 @@ static void define_pmu_regs(ARMCPU *cpu) .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7, .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS, .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, - .accessfn = pmreg_access }, + .accessfn = pmreg_access_xevcntr }, { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)), - .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access, + .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access_xevcntr, .type = ARM_CP_IO, .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn, .raw_readfn = pmevcntr_rawread,
The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however, we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well. Signed-off-by: Alex Zuepke <alex.zuepke@tum.de> --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)