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[PULL,v2,30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()

Message ID 20220422003656.1648121-31-alistair.francis@opensource.wdc.com
State New
Headers show
Series [PULL,v2,01/31] hw/ssi: Add Ibex SPI device model | expand

Commit Message

Alistair Francis April 22, 2022, 12:36 a.m. UTC 
From: Bin Meng <bin.meng@windriver.com>

This is now used by RISC-V as well. Update the comments.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/core/tcg-cpu-ops.h | 1 +
 1 file changed, 1 insertion(+)
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Patch

diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index fbe6b76764..78c6c6635d 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@  struct TCGCPUOps {
     /**
      * @debug_check_watchpoint: return true if the architectural
      * watchpoint whose address has matched should really fire, used by ARM
+     * and RISC-V
      */
     bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);