| Message ID | 20220224134901.500007-5-amir.gonnen@neuroblade.ai |
|---|---|
| State | New |
| Headers | show |
| Series | target/nios2: Shadow register set, EIC and VIC | expand |
On Thu, 24 Feb 2022 at 13:50, Amir Gonnen <amir.gonnen@neuroblade.ai> wrote: > > Demonstrate how to use nios2 VIC on a machine. > Introduce a new machine "10m50-ghrd-vic" which is based on "10m50-ghrd" > with a VIC attached and internal interrupt controller removed. > > When VIC is present, irq0 connects the VIC to the cpu, intc_present > is set to false to disable the internal interrupt controller, and the > devices on the machine are attached to the VIC (and not directly to cpu). > To allow VIC update EIC fields, we set the "cpu" property of the VIC > with a reference to the nios2 cpu. > > Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> Is a VIC a configurable option on the real hardware (well, FPGA image, I guess) that this board is modelling ? I couldn't find any docs on it with a quick google. Also, I wonder if we should have a vic machine option to the machine rather than creating a whole new machine type? thanks -- PMM
Hi Peter, > Is a VIC a configurable option on the real hardware (well, FPGA image, I guess) that this board is modelling ? > I couldn't find any docs on it with a quick google. This specific example-board from Intel does not provide a VIC option, as far as I know. (https://fpgacloud.intel.com/devstore/platform/15.1.0/Standard/max10-10m50-development-kit-ghrd-with-nios-iiddr3qspi-flashethernetmsgdmauartadc-with-linux/) Unfortunately, I couldn't find a publicly available nios2 board with a VIC. I've added "10m50-ghrd-vic" as an example to demonstrate how to wire VIC. In practice, we use Intel tooling (Quartus Prime) to generate both the hardware (nios2 + vic + other devices) and the software BSP that works with it. That is probably the regular workflow. Since nios2 is a "soft" cpu on an FPGA, each one generates their own custom "board" wired with the devices they need, memories etc. In the future I may be able to share Neuroblade's QEMU nios2 board because it is quite generic - it consumes a device tree, parses it, and wires devices according to it, so it can automatically match the generated HW. > Also, I wonder if we should have a vic machine option to the machine rather than creating a whole new machine type? Sure, if you think it makes more sense. How do you suggest doing that? A class property for the nios2 machine class? Or is there some other standard way for adding a machine specific option? Thanks, Amir The contents of this email message and any attachments are intended solely for the addressee(s) and may contain confidential and/or privileged information and may be legally protected from disclosure. If you are not the intended recipient of this message or their agent, or if this message has been addressed to you in error, please immediately alert the sender by reply email and then delete this message and any attachments. If you are not the intended recipient, you are hereby notified that any use, dissemination, copying, or storage of this message or its attachments is strictly prohibited.
diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 3d1205b8bd..9f62a2993f 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -36,10 +36,23 @@ #include "boot.h" +#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") +typedef struct Nios2MachineClass Nios2MachineClass; +DECLARE_OBJ_CHECKERS(MachineState, Nios2MachineClass, + NIOS2_MACHINE, TYPE_NIOS2_MACHINE) + #define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb" +struct Nios2MachineClass { + MachineClass parent_obj; + + bool vic; +}; + static void nios2_10m50_ghrd_init(MachineState *machine) { + Nios2MachineClass *nmc = NIOS2_MACHINE_GET_CLASS(machine); + Nios2CPU *cpu; DeviceState *dev; MemoryRegion *address_space_mem = get_system_memory(); @@ -74,8 +87,24 @@ static void nios2_10m50_ghrd_init(MachineState *machine) /* Create CPU -- FIXME */ cpu = NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - for (i = 0; i < 32; i++) { - irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + + if (nmc->vic) { + DeviceState *dev = qdev_new("nios2-vic"); + + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + cpu->intc_present = false; + qemu_irq cpu_irq = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", 0); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); + for (int i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in(dev, i); + } + MemoryRegion *dev_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr); + } else { + for (i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + } } /* Register: Altera 16550 UART */ @@ -105,11 +134,38 @@ static void nios2_10m50_ghrd_init(MachineState *machine) BINARY_DEVICE_TREE_FILE, NULL); } -static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) +static void nios2_10m50_ghrd_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc = MACHINE_CLASS(oc); + Nios2MachineClass *nmc = NIOS2_MACHINE_CLASS(oc); mc->desc = "Altera 10M50 GHRD Nios II design"; mc->init = nios2_10m50_ghrd_init; mc->is_default = true; + nmc->vic = false; } -DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); +static void nios2_10m50_ghrd_vic_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + Nios2MachineClass *nmc = NIOS2_MACHINE_CLASS(oc); + mc->desc = "Altera 10M50 GHRD Nios II design with VIC"; + mc->init = nios2_10m50_ghrd_init; + mc->is_default = false; + nmc->vic = true; +} + +static const TypeInfo nios_machine_types[] = { + { + .name = MACHINE_TYPE_NAME("10m50-ghrd"), + .parent = TYPE_MACHINE, + .class_size = sizeof(Nios2MachineClass), + .class_init = nios2_10m50_ghrd_machine_class_init, + }, { + .name = MACHINE_TYPE_NAME("10m50-ghrd-vic"), + .parent = TYPE_MACHINE, + .class_size = sizeof(Nios2MachineClass), + .class_init = nios2_10m50_ghrd_vic_machine_class_init, + } +}; + +DEFINE_TYPES(nios_machine_types)
Demonstrate how to use nios2 VIC on a machine. Introduce a new machine "10m50-ghrd-vic" which is based on "10m50-ghrd" with a VIC attached and internal interrupt controller removed. When VIC is present, irq0 connects the VIC to the cpu, intc_present is set to false to disable the internal interrupt controller, and the devices on the machine are attached to the VIC (and not directly to cpu). To allow VIC update EIC fields, we set the "cpu" property of the VIC with a reference to the nios2 cpu. Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai> --- hw/nios2/10m50_devboard.c | 64 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 60 insertions(+), 4 deletions(-) -- 2.25.1 The contents of this email message and any attachments are intended solely for the addressee(s) and may contain confidential and/or privileged information and may be legally protected from disclosure. If you are not the intended recipient of this message or their agent, or if this message has been addressed to you in error, please immediately alert the sender by reply email and then delete this message and any attachments. If you are not the intended recipient, you are hereby notified that any use, dissemination, copying, or storage of this message or its attachments is strictly prohibited.