| Message ID | 20220110061321.4040589-2-alistair.francis@opensource.wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [1/2] riscv: opentitan: fixup plic stride len | expand |
On Mon, Jan 10, 2022 at 4:13 PM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Wilfred Mallawa <wilfred.mallawa@wdc.com> > > The following changes: > 1. Fixes the incorrectly set CTRL register address. As > per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table > > The CTRL register is @ 0x04. > > This was found when attempting to fixup a bug where a timer_interrupt > was not serviced on TockOS-OpenTitan. > > 2. Adds ALERT_TEST register as documented on [1], adding repective > switch cases to error handle and later implement functionality. > > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/timer/ibex_timer.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c > index 66e1f8e48c..096588ac8a 100644 > --- a/hw/timer/ibex_timer.c > +++ b/hw/timer/ibex_timer.c > @@ -34,7 +34,9 @@ > #include "target/riscv/cpu.h" > #include "migration/vmstate.h" > > -REG32(CTRL, 0x00) > +REG32(ALERT_TEST, 0x00) > + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1) > +REG32(CTRL, 0x04) > FIELD(CTRL, ACTIVE, 0, 1) > REG32(CFG0, 0x100) > FIELD(CFG0, PRESCALE, 0, 12) > @@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr, > uint64_t retvalue = 0; > > switch (addr >> 2) { > + case R_ALERT_TEST: > + qemu_log_mask(LOG_GUEST_ERROR, > + "Attempted to read ALERT_TEST, a write only register"); > + break; > case R_CTRL: > retvalue = s->timer_ctrl; > break; > @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr, > uint32_t val = val64; > > switch (addr >> 2) { > + case R_ALERT_TEST: > + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); > + break; > case R_CTRL: > s->timer_ctrl = val; > break; > -- > 2.34.1 >
On Mon, Jan 10, 2022 at 2:13 PM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Wilfred Mallawa <wilfred.mallawa@wdc.com> > > The following changes: > 1. Fixes the incorrectly set CTRL register address. As > per [1] https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table > > The CTRL register is @ 0x04. > > This was found when attempting to fixup a bug where a timer_interrupt > was not serviced on TockOS-OpenTitan. > > 2. Adds ALERT_TEST register as documented on [1], adding repective > switch cases to error handle and later implement functionality. > > Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> > --- > hw/timer/ibex_timer.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index 66e1f8e48c..096588ac8a 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -34,7 +34,9 @@ #include "target/riscv/cpu.h" #include "migration/vmstate.h" -REG32(CTRL, 0x00) +REG32(ALERT_TEST, 0x00) + FIELD(ALERT_TEST, FATAL_FAULT, 0, 1) +REG32(CTRL, 0x04) FIELD(CTRL, ACTIVE, 0, 1) REG32(CFG0, 0x100) FIELD(CFG0, PRESCALE, 0, 12) @@ -143,6 +145,10 @@ static uint64_t ibex_timer_read(void *opaque, hwaddr addr, uint64_t retvalue = 0; switch (addr >> 2) { + case R_ALERT_TEST: + qemu_log_mask(LOG_GUEST_ERROR, + "Attempted to read ALERT_TEST, a write only register"); + break; case R_CTRL: retvalue = s->timer_ctrl; break; @@ -186,6 +192,9 @@ static void ibex_timer_write(void *opaque, hwaddr addr, uint32_t val = val64; switch (addr >> 2) { + case R_ALERT_TEST: + qemu_log_mask(LOG_UNIMP, "Alert triggering not supported"); + break; case R_CTRL: s->timer_ctrl = val; break;