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[3/3] escc: fix STATUS_SYNC bit in R_STATUS register

Message ID 20210829100103.1950-4-mark.cave-ayland@ilande.co.uk
State New
Headers show
Series escc: fix R_STATUS when SDLC mode is enabled | expand

Commit Message

Mark Cave-Ayland Aug. 29, 2021, 10:01 a.m. UTC
After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should remain
high until the flag byte has been detected. Whilst the ESCC device doesn't yet
implement SDLC mode, without this change the active low STATUS_SYNC is constantly
asserted causing the MacOS OpenTransport extension to hang on startup as it thinks
it is constantly receiving LocalTalk responses during its initial negotiation
phase.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/char/escc.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

Peter Maydell Aug. 29, 2021, 1:01 p.m. UTC | #1
On Sun, 29 Aug 2021 at 11:04, Mark Cave-Ayland
<mark.cave-ayland@ilande.co.uk> wrote:
>
> After an SDLC "Enter hunt" command has been sent the STATUS_SYNC bit should remain
> high until the flag byte has been detected. Whilst the ESCC device doesn't yet
> implement SDLC mode, without this change the active low STATUS_SYNC is constantly
> asserted causing the MacOS OpenTransport extension to hang on startup as it thinks
> it is constantly receiving LocalTalk responses during its initial negotiation
> phase.
>
> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
> ---
>  hw/char/escc.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/char/escc.c b/hw/char/escc.c
> index 0f6957ba8b..eba6b45baa 100644
> --- a/hw/char/escc.c
> +++ b/hw/char/escc.c
> @@ -92,6 +92,7 @@
>  #define W_IVEC    2
>  #define W_RXCTRL  3
>  #define RXCTRL_RXEN    0x01
> +#define RXCTRL_HUNT    0x10
>  #define W_TXCTRL1 4
>  #define TXCTRL1_PAREN  0x01
>  #define TXCTRL1_PAREV  0x02
> @@ -508,7 +509,13 @@ static void escc_mem_write(void *opaque, hwaddr addr,
>                  break;
>              }
>              break;
> -        case W_INTR ... W_RXCTRL:
> +        case W_RXCTRL:
> +            s->wregs[s->reg] = val;
> +            if (val & RXCTRL_HUNT) {
> +                s->rregs[R_STATUS] |= STATUS_SYNC;
> +            }
> +            break;
> +        case W_INTR ... W_IVEC:
>          case W_SYNC1 ... W_TXBUF:
>          case W_MISC1 ... W_CLOCK:
>          case W_MISC2 ... W_EXTINT:

If I read the manual correctly I think strictly speaking if this
is a 0->1 transition for the SYNC bit it is supposed to generate
an interrupt. But I guess since we don't implement any of this
stuff we can ignore that...

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
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Patch

diff --git a/hw/char/escc.c b/hw/char/escc.c
index 0f6957ba8b..eba6b45baa 100644
--- a/hw/char/escc.c
+++ b/hw/char/escc.c
@@ -92,6 +92,7 @@ 
 #define W_IVEC    2
 #define W_RXCTRL  3
 #define RXCTRL_RXEN    0x01
+#define RXCTRL_HUNT    0x10
 #define W_TXCTRL1 4
 #define TXCTRL1_PAREN  0x01
 #define TXCTRL1_PAREV  0x02
@@ -508,7 +509,13 @@  static void escc_mem_write(void *opaque, hwaddr addr,
                 break;
             }
             break;
-        case W_INTR ... W_RXCTRL:
+        case W_RXCTRL:
+            s->wregs[s->reg] = val;
+            if (val & RXCTRL_HUNT) {
+                s->rregs[R_STATUS] |= STATUS_SYNC;
+            }
+            break;
+        case W_INTR ... W_IVEC:
         case W_SYNC1 ... W_TXBUF:
         case W_MISC1 ... W_CLOCK:
         case W_MISC2 ... W_EXTINT: