diff mbox series

[RFC,10/13] target/riscv: Support UXL32 for float instructions

Message ID 20210805025312.15720-11-zhiwei_liu@c-sky.com
State New
Headers show
Series Support UXL field in mstatus | expand

Commit Message

LIU Zhiwei Aug. 5, 2021, 2:53 a.m. UTC 
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
 target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc
index 9bb15fdc12..fb033ccd97 100644
--- a/target/riscv/insn_trans/trans_rvd.c.inc
+++ b/target/riscv/insn_trans/trans_rvd.c.inc
@@ -23,7 +23,7 @@  static bool trans_fld(DisasContext *ctx, arg_fld *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv addr = gpr_src(ctx, a->rs1);
+    TCGv addr = gpr_src_u(ctx, a->rs1);
     TCGv temp = NULL;
 
     if (a->imm) {
@@ -46,7 +46,7 @@  static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVD);
 
-    TCGv addr = gpr_src(ctx, a->rs1);
+    TCGv addr = gpr_src_u(ctx, a->rs1);
     TCGv temp = NULL;
 
     if (a->imm) {
diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc
index ff8e942199..4576072124 100644
--- a/target/riscv/insn_trans/trans_rvf.c.inc
+++ b/target/riscv/insn_trans/trans_rvf.c.inc
@@ -28,7 +28,7 @@  static bool trans_flw(DisasContext *ctx, arg_flw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv addr = gpr_src(ctx, a->rs1);
+    TCGv addr = gpr_src_u(ctx, a->rs1);
     TCGv temp = NULL;
 
     if (a->imm) {
@@ -53,7 +53,7 @@  static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     REQUIRE_FPU;
     REQUIRE_EXT(ctx, RVF);
 
-    TCGv addr = gpr_src(ctx, a->rs1);
+    TCGv addr = gpr_src_u(ctx, a->rs1);
     TCGv temp = NULL;
 
     if (a->imm) {