[v7,67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

From: Frank Chang <frank.chang@sifive.com>

From: frank.chang@sifive.com
To: qemu-devel@nongnu.org,
	qemu-riscv@nongnu.org
Subject: [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when
 writing vector CSRs
Date: Fri, 26 Feb 2021 11:18:51 +0800
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X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,
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Cc: Frank Chang <frank.chang@sifive.com>,
 Alistair Francis <Alistair.Francis@wdc.com>,
 Palmer Dabbelt <palmer@dabbelt.com>,
 Sagar Karandikar <sagark@eecs.berkeley.edu>,
 Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
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Message ID	20210226031902.23656-68-frank.chang@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v7 67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs Date: Fri, 26 Feb 2021 11:18:51 +0800 Message-Id: <20210226031902.23656-68-frank.chang@sifive.com> In-Reply-To: <20210226031902.23656-1-frank.chang@sifive.com> References: <20210226031902.23656-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=frank.chang@sifive.com; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	support vector extension v1.0 \| expand [v7,00/75] support vector extension v1.0 [v7,01/75] target/riscv: drop vector 0.7.1 and add 1.0 support [v7,02/75] target/riscv: Use FIELD_EX32() to extract wd field [v7,03/75] target/riscv: rvv-1.0: add mstatus VS field [v7,04/75] target/riscv: rvv-1.0: add sstatus VS field [v7,05/75] target/riscv: rvv-1.0: introduce writable misa.v field [v7,06/75] target/riscv: rvv-1.0: add translation-time vector context status [v7,07/75] target/riscv: rvv-1.0: remove rvv related codes from fcsr registers [v7,08/75] target/riscv: rvv-1.0: add vcsr register [v7,09/75] target/riscv: rvv-1.0: add vlenb register [v7,10/75] target/riscv: rvv-1.0: check MSTATUS_VS when accessing vector csr registers [v7,11/75] target/riscv: rvv-1.0: remove MLEN calculations [v7,12/75] target/riscv: rvv-1.0: add fractional LMUL [v7,13/75] target/riscv: rvv-1.0: add VMA and VTA [v7,14/75] target/riscv: rvv-1.0: update check functions [v7,15/75] target/riscv: introduce more imm value modes in translator functions [v7,16/75] target/riscv: rvv:1.0: add translation-time nan-box helper function [v7,17/75] target/riscv: rvv-1.0: configure instructions [v7,18/75] target/riscv: rvv-1.0: stride load and store instructions [v7,19/75] target/riscv: rvv-1.0: index load and store instructions [v7,20/75] target/riscv: rvv-1.0: fix address index overflow bug of indexed load/store insns [v7,21/75] target/riscv: rvv-1.0: fault-only-first unit stride load [v7,22/75] target/riscv: rvv-1.0: amo operations [v7,23/75] target/riscv: rvv-1.0: load/store whole register instructions [v7,24/75] target/riscv: rvv-1.0: update vext_max_elems() for load/store insns [v7,25/75] target/riscv: rvv-1.0: take fractional LMUL into vector max elements calculation [v7,26/75] target/riscv: rvv-1.0: floating-point square-root instruction [v7,27/75] target/riscv: rvv-1.0: floating-point classify instructions [v7,28/75] target/riscv: rvv-1.0: mask population count instruction [v7,29/75] target/riscv: rvv-1.0: find-first-set mask bit instruction [v7,30/75] target/riscv: rvv-1.0: set-X-first mask bit instructions [v7,31/75] target/riscv: rvv-1.0: iota instruction [v7,32/75] target/riscv: rvv-1.0: element index instruction [v7,33/75] target/riscv: rvv-1.0: allow load element with sign-extended [v7,34/75] target/riscv: rvv-1.0: register gather instructions [v7,35/75] target/riscv: rvv-1.0: integer scalar move instructions [v7,36/75] target/riscv: rvv-1.0: floating-point move instruction [v7,37/75] target/riscv: rvv-1.0: floating-point scalar move instructions [v7,38/75] target/riscv: rvv-1.0: whole register move instructions [v7,39/75] target/riscv: rvv-1.0: integer extension instructions [v7,40/75] target/riscv: rvv-1.0: single-width averaging add and subtract instructions [v7,41/75] target/riscv: rvv-1.0: single-width bit shift instructions [v7,42/75] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow [v7,43/75] target/riscv: rvv-1.0: narrowing integer right shift instructions [v7,44/75] target/riscv: rvv-1.0: widening integer multiply-add instructions [v7,45/75] target/riscv: rvv-1.0: single-width saturating add and subtract instructions [v7,46/75] target/riscv: rvv-1.0: integer comparison instructions [v7,47/75] target/riscv: rvv-1.0: floating-point compare instructions [v7,48/75] target/riscv: rvv-1.0: mask-register logical instructions [v7,49/75] target/riscv: rvv-1.0: slide instructions [v7,50/75] target/riscv: rvv-1.0: floating-point slide instructions [v7,51/75] target/riscv: rvv-1.0: narrowing fixed-point clip instructions [v7,52/75] target/riscv: rvv-1.0: single-width floating-point reduction [v7,53/75] target/riscv: rvv-1.0: widening floating-point reduction instructions [v7,54/75] target/riscv: rvv-1.0: single-width scaling shift instructions [v7,55/75] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add [v7,56/75] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf [v7,57/75] target/riscv: rvv-1.0: remove integer extract instruction [v7,58/75] target/riscv: rvv-1.0: floating-point min/max instructions [v7,59/75] target/riscv: introduce floating-point rounding mode enum [v7,60/75] target/riscv: rvv-1.0: floating-point/integer type-convert instructions [v7,61/75] target/riscv: rvv-1.0: widening floating-point/integer type-convert [v7,62/75] target/riscv: add "set round to odd" rounding mode helper function [v7,63/75] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert [v7,64/75] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits [v7,65/75] target/riscv: rvv-1.0: implement vstart CSR [v7,66/75] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid [v7,67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs [v7,68/75] target/riscv: gdb: support vector registers for rv64 & rv32 [v7,69/75] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction [v7,70/75] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction [v7,71/75] target/riscv: set mstatus.SD bit when writing fp CSRs [v7,72/75] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 [v7,73/75] target/riscv: rvv-1.0: add vsetivli instruction [v7,74/75] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() [v7,75/75] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns

[v7,67/75] target/riscv: rvv-1.0: set mstatus.SD bit when writing vector CSRs

Commit Message

Patch