| Message ID | 20201215064631.30504-1-jiaxun.yang@flygoat.com |
|---|---|
| State | New |
| Headers | show |
| Series | MIPS Bootloader helper | expand |
On 12/15/20 7:46 AM, Jiaxun Yang wrote: > Translate embedded assembly into IO writes which is more > readable. > > Also hardcode cm_base at boot time instead of reading from CP0. > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > hw/mips/boston.c | 45 ++++++++++++--------------------------------- > 1 file changed, 12 insertions(+), 33 deletions(-) > > diff --git a/hw/mips/boston.c b/hw/mips/boston.c > index b622222c7d..9f08aa7285 100644 > --- a/hw/mips/boston.c > +++ b/hw/mips/boston.c > @@ -281,42 +281,21 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, > const uint32_t gic_base = 0x16120000; > const uint32_t cpc_base = 0x16200000; > > - /* Move CM GCRs */ > if (is_64b) { > - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ > - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ > + bl_gen_write_u64(&p, cm_base, > + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); > + bl_gen_write_u64(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); > + bl_gen_write_u64(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); > } else { > - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ > - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ > + bl_gen_write_u32(&p, cm_base, > + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); > + bl_gen_write_u32(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); > + bl_gen_write_u32(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); > } What about simplifying adding bl_gen_write_target_ulong() or bl_gen_write_ulong()?
On Wed, Jan 6, 2021 at 6:28 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > On 12/15/20 7:46 AM, Jiaxun Yang wrote: > > Translate embedded assembly into IO writes which is more > > readable. > > > > Also hardcode cm_base at boot time instead of reading from CP0. > > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > --- > > hw/mips/boston.c | 45 ++++++++++++--------------------------------- > > 1 file changed, 12 insertions(+), 33 deletions(-) > > > > diff --git a/hw/mips/boston.c b/hw/mips/boston.c > > index b622222c7d..9f08aa7285 100644 > > --- a/hw/mips/boston.c > > +++ b/hw/mips/boston.c > > @@ -281,42 +281,21 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, > > const uint32_t gic_base = 0x16120000; > > const uint32_t cpc_base = 0x16200000; > > > > - /* Move CM GCRs */ > > if (is_64b) { > > - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ > > - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ > > + bl_gen_write_u64(&p, cm_base, > > + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); > > + bl_gen_write_u64(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); > > + bl_gen_write_u64(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); > > } else { > > - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ > > - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ > > + bl_gen_write_u32(&p, cm_base, > > + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); > > + bl_gen_write_u32(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); > > + bl_gen_write_u32(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); > > } > > What about simplifying adding bl_gen_write_target_ulong() or > bl_gen_write_ulong()? bl_gen_store_ulong() similarly to bl_gen_load_ulong()?
On Wed, Jan 6, 2021 at 6:30 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > On Wed, Jan 6, 2021 at 6:28 PM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote: > > On 12/15/20 7:46 AM, Jiaxun Yang wrote: > > > Translate embedded assembly into IO writes which is more > > > readable. > > > > > > Also hardcode cm_base at boot time instead of reading from CP0. > > > > > > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > > > --- > > > hw/mips/boston.c | 45 ++++++++++++--------------------------------- > > > 1 file changed, 12 insertions(+), 33 deletions(-) > > > > > > diff --git a/hw/mips/boston.c b/hw/mips/boston.c > > > index b622222c7d..9f08aa7285 100644 > > > --- a/hw/mips/boston.c > > > +++ b/hw/mips/boston.c > > > @@ -281,42 +281,21 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, > > > const uint32_t gic_base = 0x16120000; > > > const uint32_t cpc_base = 0x16200000; > > > > > > - /* Move CM GCRs */ > > > if (is_64b) { > > > - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ > > > - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ > > > + bl_gen_write_u64(&p, cm_base, > > > + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); > > > + bl_gen_write_u64(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, > > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); > > > + bl_gen_write_u64(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, > > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); > > > } else { > > > - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ > > > - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ > > > + bl_gen_write_u32(&p, cm_base, > > > + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); > > > + bl_gen_write_u32(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, > > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); > > > + bl_gen_write_u32(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, > > > + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); > > > } > > > > What about simplifying adding bl_gen_write_target_ulong() or > > bl_gen_write_ulong()? > > bl_gen_store_ulong() similarly to bl_gen_load_ulong()? bl_gen_write_ulong(). Anyway, can be done later, so: Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
diff --git a/hw/mips/boston.c b/hw/mips/boston.c index b622222c7d..9f08aa7285 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -281,42 +281,21 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, const uint32_t gic_base = 0x16120000; const uint32_t cpc_base = 0x16200000; - /* Move CM GCRs */ if (is_64b) { - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ + bl_gen_write_u64(&p, cm_base, + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); + bl_gen_write_u64(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); + bl_gen_write_u64(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); } else { - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ + bl_gen_write_u32(&p, cm_base, + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); + bl_gen_write_u32(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); + bl_gen_write_u32(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); } - stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ - stl_p(p++, 0x01094025); /* or $8, $9 */ - stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ - if (is_64b) { - stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ - } else { - stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ - } - stl_p(p++, 0x012a4025); /* or $8, $10 */ - - /* Move & enable GIC GCRs */ - stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ - stl_p(p++, 0x35290001); /* ori $9, 0x1 */ - if (is_64b) { - stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ - } else { - stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ - } - - /* Move & enable CPC GCRs */ - stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ - stl_p(p++, 0x35290001); /* ori $9, 0x1 */ - if (is_64b) { - stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ - } else { - stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ - } - /* * Setup argument registers to follow the UHI boot protocol: *
Translate embedded assembly into IO writes which is more readable. Also hardcode cm_base at boot time instead of reading from CP0. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- hw/mips/boston.c | 45 ++++++++++++--------------------------------- 1 file changed, 12 insertions(+), 33 deletions(-)