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Tue, 15 Dec 2020 01:42:15 -0500 (EST) Received: from [148.251.23.173] (ml.mymailcheap.com [148.251.23.173]) by mail20.mymailcheap.com (Postfix) with ESMTP id AEC0542D0B; Tue, 15 Dec 2020 06:42:13 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=@flygoat.com header.b="BD8+hgjh"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id BF57F40026; Tue, 15 Dec 2020 06:42:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014531; bh=BywRbk7fBtvY251r/H3j4PpBjmNOhVX4sj3Z7oRtv3k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BD8+hgjhnmIWEMRZbec6uy5iL5Lo6FSFuLaryEI/to80Yv2QvIgIJW0jWs/rl0sVn zDLQ0a+W4unm39Dej39u69q+JSn8iT35vr1JNuGCz/fbnK8AMv+e9J7ceiOLt3oNWc 0tI/HCGXgI4KstjYmbDnnbzcIPyunndwAGhl7smA= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 1/8] hw/mips: Make bootloader addresses unsgined Date: Tue, 15 Dec 2020 14:41:53 +0800 Message-Id: <20201215064200.28751-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; 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Signed-off-by: Jiaxun Yang Tested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé --- hw/mips/fuloong2e.c | 12 ++++++------ hw/mips/malta.c | 22 +++++++++++----------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 45c596f4fe..fc4d7f21ed 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -107,9 +107,9 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, va_end(ap); } -static int64_t load_kernel(CPUMIPSState *env) +static uint64_t load_kernel(CPUMIPSState *env) { - int64_t kernel_entry, kernel_high, initrd_size; + uint64_t kernel_entry, kernel_high, initrd_size; int index = 0; long kernel_size; ram_addr_t initrd_offset; @@ -118,8 +118,8 @@ static int64_t load_kernel(CPUMIPSState *env) kernel_size = load_elf(loaderparams.kernel_filename, NULL, cpu_mips_kseg0_to_phys, NULL, - (uint64_t *)&kernel_entry, NULL, - (uint64_t *)&kernel_high, NULL, + &kernel_entry, NULL, + &kernel_high, NULL, 0, EM_MIPS, 1, 0); if (kernel_size < 0) { error_report("could not load kernel '%s': %s", @@ -180,7 +180,7 @@ static int64_t load_kernel(CPUMIPSState *env) } static void write_bootloader(CPUMIPSState *env, uint8_t *base, - int64_t kernel_addr) + uint64_t kernel_addr) { uint32_t *p; @@ -294,7 +294,7 @@ static void mips_fuloong2e_init(MachineState *machine) MemoryRegion *bios = g_new(MemoryRegion, 1); long bios_size; uint8_t *spd_data; - int64_t kernel_entry; + uint64_t kernel_entry; PCIDevice *pci_dev; PCIBus *pci_bus; ISABus *isa_bus; diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 366f4fdfcd..7db009a3e9 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -616,8 +616,8 @@ static void network_init(PCIBus *pci_bus) } } -static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, - int64_t kernel_entry) +static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, + uint64_t kernel_entry) { uint16_t *p; @@ -840,8 +840,8 @@ static void write_bootloader_nanomips(uint8_t *base, int64_t run_addr, * a2 - 32-bit address of the environment variables table * a3 - RAM size in bytes */ -static void write_bootloader(uint8_t *base, int64_t run_addr, - int64_t kernel_entry) +static void write_bootloader(uint8_t *base, uint64_t run_addr, + uint64_t kernel_entry) { uint32_t *p; @@ -1003,7 +1003,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, const char *string, ...) { va_list ap; - int32_t table_addr; + uint32_t table_addr; if (index >= ENVP_NB_ENTRIES) { return; @@ -1014,7 +1014,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, return; } - table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; + table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; prom_buf[index] = tswap32(ENVP_ADDR + table_addr); va_start(ap, string); @@ -1023,9 +1023,9 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, } /* Kernel */ -static int64_t load_kernel(void) +static uint64_t load_kernel(void) { - int64_t kernel_entry, kernel_high, initrd_size; + uint64_t kernel_entry, kernel_high, initrd_size; long kernel_size; ram_addr_t initrd_offset; int big_endian; @@ -1042,8 +1042,8 @@ static int64_t load_kernel(void) kernel_size = load_elf(loaderparams.kernel_filename, NULL, cpu_mips_kseg0_to_phys, NULL, - (uint64_t *)&kernel_entry, NULL, - (uint64_t *)&kernel_high, NULL, big_endian, EM_MIPS, + &kernel_entry, NULL, + &kernel_high, NULL, big_endian, EM_MIPS, 1, 0); if (kernel_size < 0) { error_report("could not load kernel '%s': %s", @@ -1234,7 +1234,7 @@ void mips_malta_init(MachineState *machine) MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1); const size_t smbus_eeprom_size = 8 * 256; uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size); - int64_t kernel_entry, bootloader_run_addr; + uint64_t kernel_entry, bootloader_run_addr; PCIBus *pci_bus; ISABus *isa_bus; qemu_irq cbus_irq, i8259_irq; From patchwork Tue Dec 15 06:41:54 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1416295 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; 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a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014534; bh=/OZh+B8vNOrKFyKdQb71OsWGZrCd3gaIXARjV0Oa1bA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EKxuAZXCWx8KhalMhELM0uemxUltWwzHEvfV0jIynC8BdNygHbie+2FyRby41iBQi wg+q+KT9/uaZtm1FYmlPZIk5LJ2NIi8hvXTFjwi8eq8aw7zx1bNJUszWVCmrCUxuGV sQMusJU59H06CCBKrnmf1BEDzPAnc6f/qQF2Qzzs= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 2/8] hw/mips/malta: Use address translation helper to calculate bootloader_run_addr Date: Tue, 15 Dec 2020 14:41:54 +0800 Message-Id: <20201215064200.28751-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[flygoat.com:s=default]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; 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Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 7db009a3e9..1fbb8a3220 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1302,9 +1302,9 @@ void mips_malta_init(MachineState *machine) /* For KVM we reserve 1MB of RAM for running bootloader */ if (kvm_enabled()) { ram_low_size -= 0x100000; - bootloader_run_addr = 0x40000000 + ram_low_size; + bootloader_run_addr = cpu_mips_kvm_um_phys_to_kseg0(NULL, ram_low_size); } else { - bootloader_run_addr = 0xbfc00000; + bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS); } /* Write a small bootloader to the flash location. */ From patchwork Tue Dec 15 06:41:55 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1416296 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 1FF0540026; Tue, 15 Dec 2020 06:42:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014537; bh=y6ctQgUVU5gcTG+wXv4vT3vKt925fZLwcV3fkk1kHxg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AfFEY/j7dwMMfgFulrF801N7zac6hRwL55pczu32muUzoLey0Xgi1evzo46uKSFk2 53Dlu/kgRwYUezmYeeEijJJb/rQLMXjEXZEvIjQVcDIQAEIIzYQNemVjrq9F4Odh/S SAh2exTeoVoVuxK9DTN40HmLvtXoLREzEdxbsySY= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 3/8] hw/mips: Use address translation helper to handle ENVP_ADDR Date: Tue, 15 Dec 2020 14:41:55 +0800 Message-Id: <20201215064200.28751-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; 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Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé --- hw/mips/fuloong2e.c | 24 +++++++++--------- hw/mips/malta.c | 62 ++++++++++++++++++++++----------------------- 2 files changed, 43 insertions(+), 43 deletions(-) diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index fc4d7f21ed..64cd4b98ca 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -49,7 +49,8 @@ #define DEBUG_FULOONG2E_INIT -#define ENVP_ADDR 0x80002000l +#define ENVP_PADDR 0x2000 +#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) #define ENVP_NB_ENTRIES 16 #define ENVP_ENTRY_SIZE 256 @@ -100,7 +101,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, } table_addr = sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; - prom_buf[index] = tswap32(ENVP_ADDR + table_addr); + prom_buf[index] = tswap32(ENVP_VADDR + table_addr); va_start(ap, string); vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); @@ -172,8 +173,7 @@ static uint64_t load_kernel(CPUMIPSState *env) prom_set(prom_buf, index++, "modetty0=38400n8r"); prom_set(prom_buf, index++, NULL); - rom_add_blob_fixed("prom", prom_buf, prom_size, - cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); + rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); g_free(prom_buf); return kernel_entry; @@ -199,14 +199,14 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base, stl_p(p++, 0x3c040000); /* ori a0, a0, 2 */ stl_p(p++, 0x34840002); - /* lui a1, high(ENVP_ADDR) */ - stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); - /* ori a1, a0, low(ENVP_ADDR) */ - stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); - /* lui a2, high(ENVP_ADDR + 8) */ - stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); - /* ori a2, a2, low(ENVP_ADDR + 8) */ - stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); + /* lui a1, high(ENVP_VADDR) */ + stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff)); + /* ori a1, a0, low(ENVP_VADDR) */ + stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff)); + /* lui a2, high(ENVP_VADDR + 8) */ + stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff)); + /* ori a2, a2, low(ENVP_VADDR + 8) */ + stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff)); /* lui a3, high(env->ram_size) */ stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); /* ori a3, a3, low(env->ram_size) */ diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 1fbb8a3220..9afc0b427b 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -62,7 +62,8 @@ #include "hw/mips/cps.h" #include "hw/qdev-clock.h" -#define ENVP_ADDR 0x80002000l +#define ENVP_PADDR 0x2000 +#define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR) #define ENVP_NB_ENTRIES 16 #define ENVP_ENTRY_SIZE 256 @@ -656,29 +657,29 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, /* li a0,2 */ } - stw_p(p++, 0xe3a0 | NM_HI1(ENVP_ADDR - 64)); + stw_p(p++, 0xe3a0 | NM_HI1(ENVP_VADDR - 64)); - stw_p(p++, NM_HI2(ENVP_ADDR - 64)); - /* lui sp,%hi(ENVP_ADDR - 64) */ + stw_p(p++, NM_HI2(ENVP_VADDR - 64)); + /* lui sp,%hi(ENVP_VADDR - 64) */ - stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_ADDR - 64)); - /* ori sp,sp,%lo(ENVP_ADDR - 64) */ + stw_p(p++, 0x83bd); stw_p(p++, NM_LO(ENVP_VADDR - 64)); + /* ori sp,sp,%lo(ENVP_VADDR - 64) */ - stw_p(p++, 0xe0a0 | NM_HI1(ENVP_ADDR)); + stw_p(p++, 0xe0a0 | NM_HI1(ENVP_VADDR)); - stw_p(p++, NM_HI2(ENVP_ADDR)); - /* lui a1,%hi(ENVP_ADDR) */ + stw_p(p++, NM_HI2(ENVP_VADDR)); + /* lui a1,%hi(ENVP_VADDR) */ - stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_ADDR)); - /* ori a1,a1,%lo(ENVP_ADDR) */ + stw_p(p++, 0x80a5); stw_p(p++, NM_LO(ENVP_VADDR)); + /* ori a1,a1,%lo(ENVP_VADDR) */ - stw_p(p++, 0xe0c0 | NM_HI1(ENVP_ADDR + 8)); + stw_p(p++, 0xe0c0 | NM_HI1(ENVP_VADDR + 8)); - stw_p(p++, NM_HI2(ENVP_ADDR + 8)); - /* lui a2,%hi(ENVP_ADDR + 8) */ + stw_p(p++, NM_HI2(ENVP_VADDR + 8)); + /* lui a2,%hi(ENVP_VADDR + 8) */ - stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_ADDR + 8)); - /* ori a2,a2,%lo(ENVP_ADDR + 8) */ + stw_p(p++, 0x80c6); stw_p(p++, NM_LO(ENVP_VADDR + 8)); + /* ori a2,a2,%lo(ENVP_VADDR + 8) */ stw_p(p++, 0xe0e0 | NM_HI1(loaderparams.ram_low_size)); @@ -878,18 +879,18 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ } - /* lui sp, high(ENVP_ADDR) */ - stl_p(p++, 0x3c1d0000 | (((ENVP_ADDR - 64) >> 16) & 0xffff)); - /* ori sp, sp, low(ENVP_ADDR) */ - stl_p(p++, 0x37bd0000 | ((ENVP_ADDR - 64) & 0xffff)); - /* lui a1, high(ENVP_ADDR) */ - stl_p(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); - /* ori a1, a1, low(ENVP_ADDR) */ - stl_p(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); - /* lui a2, high(ENVP_ADDR + 8) */ - stl_p(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); - /* ori a2, a2, low(ENVP_ADDR + 8) */ - stl_p(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); + /* lui sp, high(ENVP_VADDR) */ + stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff)); + /* ori sp, sp, low(ENVP_VADDR) */ + stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff)); + /* lui a1, high(ENVP_VADDR) */ + stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff)); + /* ori a1, a1, low(ENVP_VADDR) */ + stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff)); + /* lui a2, high(ENVP_VADDR + 8) */ + stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff)); + /* ori a2, a2, low(ENVP_VADDR + 8) */ + stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff)); /* lui a3, high(ram_low_size) */ stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); /* ori a3, a3, low(ram_low_size) */ @@ -1015,7 +1016,7 @@ static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t *prom_buf, int index, } table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE; - prom_buf[index] = tswap32(ENVP_ADDR + table_addr); + prom_buf[index] = tswap32(ENVP_VADDR + table_addr); va_start(ap, string); vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap); @@ -1122,8 +1123,7 @@ static uint64_t load_kernel(void) prom_set(prom_buf, prom_index++, "38400n8r"); prom_set(prom_buf, prom_index++, NULL); - rom_add_blob_fixed("prom", prom_buf, prom_size, - cpu_mips_kseg0_to_phys(NULL, ENVP_ADDR)); + rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR); g_free(prom_buf); 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Tue, 15 Dec 2020 01:45:23 -0500 (EST) Received: from [148.251.23.173] (ml.mymailcheap.com [148.251.23.173]) by mail20.mymailcheap.com (Postfix) with ESMTP id 8349D41001; Tue, 15 Dec 2020 06:45:22 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=@flygoat.com header.b="GnaJyb6d"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 59506403B9; Tue, 15 Dec 2020 06:45:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014717; bh=eGnooaniH90/48CtMlnOSMVavirfnaDqTaKTCdxxx9w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GnaJyb6dI3FWaRBY7MGusQ2FI2sGekLCVt1VAy7ZV3edRZMvAL/QRDa2wn41XdLcb xUWfJd2I0bsUoSVO0MgAScEaOcYnrvoweZQ7lT9Sr9/JP29D/RImrdM2or1YEsThCU 8pg+1ASqz1aaLXaP1waS/ZW1fwYI3LQjyJqNbzGs= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 4/8] hw/mips: Add a bootloader helper Date: Tue, 15 Dec 2020 14:45:04 +0800 Message-Id: <20201215064507.30148-1-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[flygoat.com:s=default]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; BROKEN_CONTENT_TYPE(1.50)[]; R_SPF_SOFTFAIL(0.00)[~all:c]; RCPT_COUNT_FIVE(0.00)[5]; ML_SERVERS(-3.10)[148.251.23.173]; DKIM_TRACE(0.00)[flygoat.com:+]; DMARC_POLICY_ALLOW(0.00)[flygoat.com,none]; MID_CONTAINS_FROM(1.00)[]; DMARC_POLICY_ALLOW_WITH_FAILURES(0.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:148.251.0.0/16, country:DE]; RCVD_COUNT_TWO(0.00)[2]; HFILTER_HELO_BAREIP(3.00)[148.251.23.173,1] X-Rspamd-Queue-Id: 8349D41001 X-Spam: Yes Received-SPF: pass client-ip=144.217.248.102; envelope-from=jiaxun.yang@flygoat.com; helo=relay1.mymailcheap.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_SORBS_WEB=1.5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiaxun Yang , chenhuacai@kernel.org, f4bug@amsat.org, paulburton@kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Add a bootloader helper to generate simple bootloaders for kernel. It can help us reduce inline hex hack and also keep MIPS release 6 compatibility easier. Signed-off-by: Jiaxun Yang --- hw/mips/bootloader.c | 157 +++++++++++++++++++++++++++++++++++ hw/mips/meson.build | 2 +- include/hw/mips/bootloader.h | 48 +++++++++++ 3 files changed, 206 insertions(+), 1 deletion(-) create mode 100644 hw/mips/bootloader.c create mode 100644 include/hw/mips/bootloader.h diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c new file mode 100644 index 0000000000..97916ffd24 --- /dev/null +++ b/hw/mips/bootloader.c @@ -0,0 +1,157 @@ +/* + * Utility for QEMU MIPS to generate it's simple bootloader + * + * Instructions used here are carefully selected to keep compatibility with + * MIPS Release 6. + * + * Copyright (C) 2020 Jiaxun Yang + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "hw/mips/bootloader.h" + +/* Base types */ +static void bl_gen_nop(uint32_t **p) +{ + stl_p(*p, 0); + *p = *p + 1; +} + +static void bl_gen_r_type(uint32_t **p, uint8_t opcode, bl_reg rs, bl_reg rt, + bl_reg rd, uint8_t shift, uint8_t funct) +{ + uint32_t insn = 0; + + insn = deposit32(insn, 26, 6, opcode); + insn = deposit32(insn, 21, 5, rs); + insn = deposit32(insn, 16, 5, rt); + insn = deposit32(insn, 11, 5, rd); + insn = deposit32(insn, 6, 5, shift); + insn = deposit32(insn, 0, 6, funct); + + stl_p(*p, insn); + *p = *p + 1; +} + +static void bl_gen_i_type(uint32_t **p, uint8_t opcode, bl_reg rs, bl_reg rt, + uint16_t imm) +{ + uint32_t insn = 0; + + insn = deposit32(insn, 26, 6, opcode); + insn = deposit32(insn, 21, 5, rs); + insn = deposit32(insn, 16, 5, rt); + insn = deposit32(insn, 0, 16, imm); + + stl_p(*p, insn); + *p = *p + 1; +} + +static bool bootcpu_supports_isa(uint64_t isa_mask) +{ + return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask); +} + +/* Single instructions */ +static void bl_gen_dsll(uint32_t **p, bl_reg rd, bl_reg rt, uint8_t sa) +{ + if (bootcpu_supports_isa(ISA_MIPS3)) { + bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38); + } else { + g_assert_not_reached(); /* unsupported */ + } +} + +static void bl_gen_jalr(uint32_t **p, bl_reg rs) +{ + bl_gen_r_type(p, 0, rs, 0, BL_REG_RA, 0, 0x9); +} + +static void bl_gen_lui(uint32_t **p, bl_reg rt, uint16_t imm) +{ + /* R6: It's a alias of AUI with RS = 0 */ + bl_gen_i_type(p, 0xf, 0, rt, imm); +} + +static void bl_gen_ori(uint32_t **p, bl_reg rt, bl_reg rs, uint16_t imm) +{ + bl_gen_i_type(p, 0xd, rs, rt, imm); +} + +static void bl_gen_sw(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset) +{ + bl_gen_i_type(p, 0x2b, base, rt, offset); +} + +static void bl_gen_sd(uint32_t **p, bl_reg rt, uint8_t base, uint16_t offset) +{ + if (bootcpu_supports_isa(ISA_MIPS3)) { + bl_gen_i_type(p, 0x3f, base, rt, offset); + } else { + g_assert_not_reached(); /* unsupported */ + } +} + +/* Pseudo instructions */ +static void bl_gen_li(uint32_t **p, bl_reg rt, uint32_t imm) +{ + bl_gen_lui(p, rt, extract32(imm, 16, 16)); + bl_gen_ori(p, rt, rt, extract32(imm, 0, 16)); +} + +static void bl_gen_dli(uint32_t **p, bl_reg rt, uint64_t imm) +{ + bl_gen_li(p, rt, extract64(imm, 32, 32)); + bl_gen_dsll(p, rt, rt, 16); + bl_gen_ori(p, rt, rt, extract64(imm, 16, 16)); + bl_gen_dsll(p, rt, rt, 16); + bl_gen_ori(p, rt, rt, extract64(imm, 0, 16)); +} + +static void bl_gen_load_ulong(uint32_t **p, bl_reg rt, target_ulong imm) +{ + if (bootcpu_supports_isa(ISA_MIPS3)) { + bl_gen_dli(p, rt, imm); /* 64bit */ + } else { + bl_gen_li(p, rt, imm); /* 32bit */ + } +} + +/* Helpers */ +void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr) +{ + bl_gen_load_ulong(p, BL_REG_T9, jump_addr); + bl_gen_jalr(p, BL_REG_T9); + bl_gen_nop(p); /* delay slot */ +} + +void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0, + target_ulong a1, target_ulong a2, target_ulong a3, + target_ulong kernel_addr) +{ + bl_gen_load_ulong(p, BL_REG_SP, sp); + bl_gen_load_ulong(p, BL_REG_A0, a0); + bl_gen_load_ulong(p, BL_REG_A1, a1); + bl_gen_load_ulong(p, BL_REG_A2, a2); + bl_gen_load_ulong(p, BL_REG_A3, a3); + + bl_gen_jump_to(p, kernel_addr); +} + +void bl_gen_write_u32(uint32_t **p, uint32_t val, target_ulong addr) +{ + bl_gen_li(p, BL_REG_K0, val); + bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_sw(p, BL_REG_K0, BL_REG_K1, 0x0); +} + +void bl_gen_write_u64(uint32_t **p, uint64_t val, target_ulong addr) +{ + bl_gen_dli(p, BL_REG_K0, val); + bl_gen_load_ulong(p, BL_REG_K1, addr); + bl_gen_sd(p, BL_REG_K0, BL_REG_K1, 0x0); +} diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 77b4d8f365..fdb783ff55 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,5 +1,5 @@ mips_ss = ss.source_set() -mips_ss.add(files('mips_int.c')) +mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) diff --git a/include/hw/mips/bootloader.h b/include/hw/mips/bootloader.h new file mode 100644 index 0000000000..96c7333b9e --- /dev/null +++ b/include/hw/mips/bootloader.h @@ -0,0 +1,48 @@ +#ifndef HW_MIPS_BOOTLOADER_H +#define HW_MIPS_BOOTLOADER_H + +#include "exec/cpu-defs.h" + +void bl_gen_jump_to(uint32_t **p, target_ulong jump_addr); +void bl_gen_jump_kernel(uint32_t **p, target_ulong sp, target_ulong a0, + target_ulong a1, target_ulong a2, target_ulong a3, + target_ulong kernel_addr); +void bl_gen_write_u32(uint32_t **p, uint32_t val, target_ulong addr); +void bl_gen_write_u64(uint32_t **p, uint64_t val, target_ulong addr); + +typedef enum bl_reg { + BL_REG_ZERO = 0, + BL_REG_AT = 1, + BL_REG_V0 = 2, + BL_REG_V1 = 3, + BL_REG_A0 = 4, + BL_REG_A1 = 5, + BL_REG_A2 = 6, + BL_REG_A3 = 7, + BL_REG_T0 = 8, + BL_REG_T1 = 9, + BL_REG_T2 = 10, + BL_REG_T3 = 11, + BL_REG_T4 = 12, + BL_REG_T5 = 13, + BL_REG_T6 = 14, + BL_REG_T7 = 15, + BL_REG_S0 = 16, + BL_REG_S1 = 17, + BL_REG_S2 = 18, + BL_REG_S3 = 19, + BL_REG_S4 = 20, + BL_REG_S5 = 21, + BL_REG_S6 = 22, + BL_REG_S7 = 23, + BL_REG_T8 = 24, + BL_REG_T9 = 25, + BL_REG_K0 = 26, + BL_REG_K1 = 27, + BL_REG_GP = 28, + BL_REG_SP = 29, + BL_REG_FP = 30, + BL_REG_RA = 31, +} bl_reg; + +#endif From patchwork Tue Dec 15 06:45:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1416302 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 22903403B9; Tue, 15 Dec 2020 06:45:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014720; bh=Tr8W+sLtPkU5Ifn7lYtOpahhe6uDBWHqDIhHMMwE6us=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=kvHZSy5OHSLIaQPvLQbCeUpaItMzB/YSzDPolL23f+jDoA85YV/R0AisEOifBV6ha k/9T1Qmaeo3868oYF2FptN9SM/gjOU+APLIIyvvAUMumKxzjsWwuFiGwV/42oSeIHW XjYiXSoFfz2RHoN/rD99tN9tmwuN8oYNu+zGt7Dk= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 5/8] hw/mips: Use bl_gen_kernel_jump to generate bootloaders Date: Tue, 15 Dec 2020 14:45:05 +0800 Message-Id: <20201215064507.30148-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; 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Signed-off-by: Jiaxun Yang --- hw/mips/boston.c | 17 ++--------------- hw/mips/fuloong2e.c | 28 ++++------------------------ hw/mips/malta.c | 41 ++++++++++------------------------------- 3 files changed, 16 insertions(+), 70 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index c3b94c68e1..b622222c7d 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -27,6 +27,7 @@ #include "hw/ide/ahci.h" #include "hw/loader.h" #include "hw/loader-fit.h" +#include "hw/mips/bootloader.h" #include "hw/mips/cps.h" #include "hw/pci-host/xilinx-pcie.h" #include "hw/qdev-clock.h" @@ -324,21 +325,7 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, * a2/$6 = 0 * a3/$7 = 0 */ - stl_p(p++, 0x2404fffe); /* li $4, -2 */ - /* lui $5, hi(fdt_addr) */ - stl_p(p++, 0x3c050000 | ((fdt_addr >> 16) & 0xffff)); - if (fdt_addr & 0xffff) { /* ori $5, lo(fdt_addr) */ - stl_p(p++, 0x34a50000 | (fdt_addr & 0xffff)); - } - stl_p(p++, 0x34060000); /* li $6, 0 */ - stl_p(p++, 0x34070000); /* li $7, 0 */ - - /* Load kernel entry address & jump to it */ - /* lui $25, hi(kernel_entry) */ - stl_p(p++, 0x3c190000 | ((kernel_entry >> 16) & 0xffff)); - /* ori $25, lo(kernel_entry) */ - stl_p(p++, 0x37390000 | (kernel_entry & 0xffff)); - stl_p(p++, 0x03200009); /* jr $25 */ + bl_gen_jump_kernel(&p, 0, (int32_t)-2, fdt_addr, 0, 0, kernel_entry); } static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 64cd4b98ca..9b0eb8a314 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -33,6 +33,7 @@ #include "hw/i2c/smbus_eeprom.h" #include "hw/block/flash.h" #include "hw/mips/mips.h" +#include "hw/mips/bootloader.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" #include "qemu/log.h" @@ -195,30 +196,9 @@ static void write_bootloader(CPUMIPSState *env, uint8_t *base, /* Second part of the bootloader */ p = (uint32_t *)(base + 0x040); - /* lui a0, 0 */ - stl_p(p++, 0x3c040000); - /* ori a0, a0, 2 */ - stl_p(p++, 0x34840002); - /* lui a1, high(ENVP_VADDR) */ - stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff)); - /* ori a1, a0, low(ENVP_VADDR) */ - stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff)); - /* lui a2, high(ENVP_VADDR + 8) */ - stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff)); - /* ori a2, a2, low(ENVP_VADDR + 8) */ - stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff)); - /* lui a3, high(env->ram_size) */ - stl_p(p++, 0x3c070000 | (loaderparams.ram_size >> 16)); - /* ori a3, a3, low(env->ram_size) */ - stl_p(p++, 0x34e70000 | (loaderparams.ram_size & 0xffff)); - /* lui ra, high(kernel_addr) */ - stl_p(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); - /* ori ra, ra, low(kernel_addr) */ - stl_p(p++, 0x37ff0000 | (kernel_addr & 0xffff)); - /* jr ra */ - stl_p(p++, 0x03e00008); - /* nop */ - stl_p(p++, 0x00000000); + bl_gen_jump_kernel(&p, ENVP_VADDR - 64, 2, ENVP_VADDR, + ENVP_VADDR + 8, loaderparams.ram_size, + kernel_addr); } static void main_cpu_reset(void *opaque) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 9afc0b427b..ffd67b8293 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -37,6 +37,7 @@ #include "hw/i2c/smbus_eeprom.h" #include "hw/block/flash.h" #include "hw/mips/mips.h" +#include "hw/mips/bootloader.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" #include "sysemu/sysemu.h" @@ -844,6 +845,7 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, static void write_bootloader(uint8_t *base, uint64_t run_addr, uint64_t kernel_entry) { + target_ulong a0; uint32_t *p; /* Small bootloader */ @@ -872,30 +874,6 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, /* Second part of the bootloader */ p = (uint32_t *) (base + 0x580); - if (semihosting_get_argc()) { - /* Preserve a0 content as arguments have been passed */ - stl_p(p++, 0x00000000); /* nop */ - } else { - stl_p(p++, 0x24040002); /* addiu a0, zero, 2 */ - } - - /* lui sp, high(ENVP_VADDR) */ - stl_p(p++, 0x3c1d0000 | (((ENVP_VADDR - 64) >> 16) & 0xffff)); - /* ori sp, sp, low(ENVP_VADDR) */ - stl_p(p++, 0x37bd0000 | ((ENVP_VADDR - 64) & 0xffff)); - /* lui a1, high(ENVP_VADDR) */ - stl_p(p++, 0x3c050000 | ((ENVP_VADDR >> 16) & 0xffff)); - /* ori a1, a1, low(ENVP_VADDR) */ - stl_p(p++, 0x34a50000 | (ENVP_VADDR & 0xffff)); - /* lui a2, high(ENVP_VADDR + 8) */ - stl_p(p++, 0x3c060000 | (((ENVP_VADDR + 8) >> 16) & 0xffff)); - /* ori a2, a2, low(ENVP_VADDR + 8) */ - stl_p(p++, 0x34c60000 | ((ENVP_VADDR + 8) & 0xffff)); - /* lui a3, high(ram_low_size) */ - stl_p(p++, 0x3c070000 | (loaderparams.ram_low_size >> 16)); - /* ori a3, a3, low(ram_low_size) */ - stl_p(p++, 0x34e70000 | (loaderparams.ram_low_size & 0xffff)); - /* Load BAR registers as done by YAMON */ stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ @@ -947,13 +925,14 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, #endif stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ - /* Jump to kernel code */ - stl_p(p++, 0x3c1f0000 | - ((kernel_entry >> 16) & 0xffff)); /* lui ra, high(kernel_entry) */ - stl_p(p++, 0x37ff0000 | - (kernel_entry & 0xffff)); /* ori ra, ra, low(kernel_entry) */ - stl_p(p++, 0x03e00009); /* jalr ra */ - stl_p(p++, 0x00000000); /* nop */ + if (semihosting_get_argc()) { + a0 = 0; + } else { + a0 = 2; + } + bl_gen_jump_kernel(&p, ENVP_VADDR - 64, a0, ENVP_VADDR, + ENVP_VADDR + 8, loaderparams.ram_low_size, + kernel_entry); /* YAMON subroutines */ p = (uint32_t *) (base + 0x800); From patchwork Tue Dec 15 06:45:06 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1416301 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 1AC46403B9; Tue, 15 Dec 2020 06:45:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014723; bh=CNQZUp/uUP92ip3oJH4DOwjwgvT3AQbjqIxo+Z3m7Bs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Pga2ORzWyib1cQchDMCyRQvKI7j4KXoVOgdMer56+wTaN4W9dyGqSWAD4vZlpBBek w2y4Ctk0KZiyxaUNATE6gAGcXZvgPkFZi+IixTUL32oJvxzCWiVeP+mkpaMY8CoPyd J/eZXwwe2JA0bjJ3YIbNhgsWZGM0KM/fztg835s0= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 6/8] target/mips/addr: Add translation helpers for KSEG1 Date: Tue, 15 Dec 2020 14:45:06 +0800 Message-Id: <20201215064507.30148-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; 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Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé Tested-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen --- target/mips/addr.c | 10 ++++++++++ target/mips/cpu.h | 2 ++ 2 files changed, 12 insertions(+) diff --git a/target/mips/addr.c b/target/mips/addr.c index 27a6036c45..86f1c129c9 100644 --- a/target/mips/addr.c +++ b/target/mips/addr.c @@ -40,6 +40,16 @@ uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr) return addr | 0x40000000ll; } +uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr) +{ + return addr & 0x1fffffffll; +} + +uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr) +{ + return (addr & 0x1fffffffll) | 0xffffffffa0000000ll; +} + bool mips_um_ksegs_enabled(void) { return mips_um_ksegs; diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3ac21d0e9c..0bb1218a57 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1303,6 +1303,8 @@ uint64_t cpu_mips_kseg0_to_phys(void *opaque, uint64_t addr); uint64_t cpu_mips_phys_to_kseg0(void *opaque, uint64_t addr); uint64_t cpu_mips_kvm_um_phys_to_kseg0(void *opaque, uint64_t addr); +uint64_t cpu_mips_kseg1_to_phys(void *opaque, uint64_t addr); +uint64_t cpu_mips_phys_to_kseg1(void *opaque, uint64_t addr); bool mips_um_ksegs_enabled(void); void mips_um_ksegs_enable(void); From patchwork Tue Dec 15 06:45:07 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1416298 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=flygoat.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=mymailcheap.com header.i=@mymailcheap.com header.a=rsa-sha256 header.s=default header.b=YIjaqRKb; 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Tue, 15 Dec 2020 01:45:32 -0500 (EST) Received: from [148.251.23.173] (ml.mymailcheap.com [148.251.23.173]) by mail20.mymailcheap.com (Postfix) with ESMTP id 7B9A8403B9; Tue, 15 Dec 2020 06:45:31 +0000 (UTC) Authentication-Results: mail20.mymailcheap.com; dkim=pass (1024-bit key; unprotected) header.d=flygoat.com header.i=@flygoat.com header.b="ksaOM1kY"; dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id B9915403B9; Tue, 15 Dec 2020 06:45:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014725; bh=zJE5fp1EqMxX8dCgYttVAKHUtea9qIzC4ou0u94Fil8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ksaOM1kYC+I13E30ArOKNQA85/IDAJWP2yfsvL1F3cmd3ztzibThwl9YYp64rKGgG SkOHSTg5qVD2caPQ2NCff/W+3ArPEl0B2xs9YIKTREzdPI8TxP47Bl0slUFLWmI7Zc Haop3C2fj9Gjoghkim+zOrrCgspT+FKZkiPfju+o= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 7/8] hw/mips/malta: Use bootloader helper to set BAR resgiters Date: Tue, 15 Dec 2020 14:45:07 +0800 Message-Id: <20201215064507.30148-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[flygoat.com:s=default]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; BROKEN_CONTENT_TYPE(1.50)[]; R_SPF_SOFTFAIL(0.00)[~all:c]; RCPT_COUNT_FIVE(0.00)[5]; ML_SERVERS(-3.10)[148.251.23.173]; DKIM_TRACE(0.00)[flygoat.com:+]; DMARC_POLICY_ALLOW(0.00)[flygoat.com,none]; MID_CONTAINS_FROM(1.00)[]; DMARC_POLICY_ALLOW_WITH_FAILURES(0.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:148.251.0.0/16, country:DE]; RCVD_COUNT_TWO(0.00)[2]; HFILTER_HELO_BAREIP(3.00)[148.251.23.173,1] X-Rspamd-Queue-Id: 7B9A8403B9 X-Spam: Yes Received-SPF: pass client-ip=144.217.248.102; envelope-from=jiaxun.yang@flygoat.com; helo=relay1.mymailcheap.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_SORBS_WEB=1.5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiaxun Yang , chenhuacai@kernel.org, f4bug@amsat.org, paulburton@kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Translate embedded assembly into IO writes which is more readable. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 68 ++++++++++++++----------------------------------- 1 file changed, 19 insertions(+), 49 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index ffd67b8293..2799bc36c7 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -875,55 +875,25 @@ static void write_bootloader(uint8_t *base, uint64_t run_addr, p = (uint32_t *) (base + 0x580); /* Load BAR registers as done by YAMON */ - stl_p(p++, 0x3c09b400); /* lui t1, 0xb400 */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c08df00); /* lui t0, 0xdf00 */ -#else - stl_p(p++, 0x340800df); /* ori t0, r0, 0x00df */ -#endif - stl_p(p++, 0xad280068); /* sw t0, 0x0068(t1) */ - - stl_p(p++, 0x3c09bbe0); /* lui t1, 0xbbe0 */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c08c000); /* lui t0, 0xc000 */ -#else - stl_p(p++, 0x340800c0); /* ori t0, r0, 0x00c0 */ -#endif - stl_p(p++, 0xad280048); /* sw t0, 0x0048(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c084000); /* lui t0, 0x4000 */ -#else - stl_p(p++, 0x34080040); /* ori t0, r0, 0x0040 */ -#endif - stl_p(p++, 0xad280050); /* sw t0, 0x0050(t1) */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c088000); /* lui t0, 0x8000 */ -#else - stl_p(p++, 0x34080080); /* ori t0, r0, 0x0080 */ -#endif - stl_p(p++, 0xad280058); /* sw t0, 0x0058(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c083f00); /* lui t0, 0x3f00 */ -#else - stl_p(p++, 0x3408003f); /* ori t0, r0, 0x003f */ -#endif - stl_p(p++, 0xad280060); /* sw t0, 0x0060(t1) */ - -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c08c100); /* lui t0, 0xc100 */ -#else - stl_p(p++, 0x340800c1); /* ori t0, r0, 0x00c1 */ -#endif - stl_p(p++, 0xad280080); /* sw t0, 0x0080(t1) */ -#ifdef TARGET_WORDS_BIGENDIAN - stl_p(p++, 0x3c085e00); /* lui t0, 0x5e00 */ -#else - stl_p(p++, 0x3408005e); /* ori t0, r0, 0x005e */ -#endif - stl_p(p++, 0xad280088); /* sw t0, 0x0088(t1) */ + /* move GT64120 registers from 0x14000000 to 0x1be00000 */ + bl_gen_write_u32(&p, cpu_to_be32(0xdf000000), + cpu_mips_phys_to_kseg1(NULL, 0x14000068)); + + /* setup MEM-to-PCI0 mapping */ + /* setup PCI0 io window to 0x18000000-0x181fffff */ + bl_gen_write_u32(&p, cpu_to_be32(0xc0000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00048)); + bl_gen_write_u32(&p, cpu_to_be32(0x40000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00050)); + /* setup PCI0 mem windows */ + bl_gen_write_u32(&p, cpu_to_be32(0x80000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00058)); + bl_gen_write_u32(&p, cpu_to_be32(0x3f000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00060)); + bl_gen_write_u32(&p, cpu_to_be32(0xc1000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00080)); + bl_gen_write_u32(&p, cpu_to_be32(0x5e000000), + cpu_mips_phys_to_kseg1(NULL, 0x1be00088)); if (semihosting_get_argc()) { a0 = 0; From patchwork Tue Dec 15 06:46:31 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 1416299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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dkim-atps=neutral AI-Spam-Status: Not processed Received: from strike.U-LINK.com (unknown [116.228.84.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail20.mymailcheap.com (Postfix) with ESMTPSA id 8F5E440026; Tue, 15 Dec 2020 06:46:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=flygoat.com; s=default; t=1608014798; bh=Mg/jh/NtAg4BAIaA2cE74QFzPqb6n/LIT/mGYdacmF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PXi8WgzwEQsXeLddkL5G/Qp78BgYsUEDU5jFGtayYgO9rCqWWjwarM0RzvJ2CsU0e ZPp6yL9r/e/ENmWubIyzmzfyxfpV5X5aaStvpUfKQkZQ0vzBcQtAlFE+qrTRJlyD4L +EhjdBTHLKYiQ81M8YITv+th9NnGhiTk8AOjWsIw= From: Jiaxun Yang To: qemu-devel@nongnu.org Subject: [PATCH v2 8/8] hw/mips/boston: Use bootloader helper to set GCRs Date: Tue, 15 Dec 2020 14:46:31 +0800 Message-Id: <20201215064631.30504-1-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.29.2 In-Reply-To: <20201215064200.28751-1-jiaxun.yang@flygoat.com> References: <20201215064200.28751-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Rspamd-Server: mail20.mymailcheap.com X-Spamd-Result: default: False [4.90 / 10.00]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; R_DKIM_ALLOW(0.00)[flygoat.com:s=default]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; R_MISSING_CHARSET(2.50)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; MIME_GOOD(-0.10)[text/plain]; BROKEN_CONTENT_TYPE(1.50)[]; R_SPF_SOFTFAIL(0.00)[~all:c]; RCPT_COUNT_FIVE(0.00)[5]; ML_SERVERS(-3.10)[213.133.102.83]; DKIM_TRACE(0.00)[flygoat.com:+]; DMARC_POLICY_ALLOW(0.00)[flygoat.com,none]; MID_CONTAINS_FROM(1.00)[]; DMARC_POLICY_ALLOW_WITH_FAILURES(0.00)[]; RCVD_NO_TLS_LAST(0.10)[]; FROM_EQ_ENVFROM(0.00)[]; MIME_TRACE(0.00)[0:+]; ASN(0.00)[asn:24940, ipnet:213.133.96.0/19, country:DE]; RCVD_COUNT_TWO(0.00)[2]; HFILTER_HELO_BAREIP(3.00)[213.133.102.83,1] X-Rspamd-Queue-Id: 0CC3140026 X-Spam: Yes Received-SPF: pass client-ip=217.182.113.132; envelope-from=jiaxun.yang@flygoat.com; helo=relay2.mymailcheap.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_SORBS_WEB=1.5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jiaxun Yang , chenhuacai@kernel.org, f4bug@amsat.org, paulburton@kernel.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Translate embedded assembly into IO writes which is more readable. Also hardcode cm_base at boot time instead of reading from CP0. Signed-off-by: Jiaxun Yang Reviewed-by: Philippe Mathieu-Daudé --- hw/mips/boston.c | 45 ++++++++++++--------------------------------- 1 file changed, 12 insertions(+), 33 deletions(-) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index b622222c7d..9f08aa7285 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -281,42 +281,21 @@ static void gen_firmware(uint32_t *p, hwaddr kernel_entry, hwaddr fdt_addr, const uint32_t gic_base = 0x16120000; const uint32_t cpc_base = 0x16200000; - /* Move CM GCRs */ if (is_64b) { - stl_p(p++, 0x40287803); /* dmfc0 $8, CMGCRBase */ - stl_p(p++, 0x00084138); /* dsll $8, $8, 4 */ + bl_gen_write_u64(&p, cm_base, + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); + bl_gen_write_u64(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); + bl_gen_write_u64(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); } else { - stl_p(p++, 0x40087803); /* mfc0 $8, CMGCRBase */ - stl_p(p++, 0x00084100); /* sll $8, $8, 4 */ + bl_gen_write_u32(&p, cm_base, + cpu_mips_phys_to_kseg1(NULL, GCR_BASE_ADDR + GCR_BASE_OFS)); + bl_gen_write_u32(&p, gic_base | GCR_GIC_BASE_GICEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_GIC_BASE_OFS)); + bl_gen_write_u32(&p, cpc_base | GCR_CPC_BASE_CPCEN_MSK, + cpu_mips_phys_to_kseg1(NULL, cm_base + GCR_CPC_BASE_OFS)); } - stl_p(p++, 0x3c09a000); /* lui $9, 0xa000 */ - stl_p(p++, 0x01094025); /* or $8, $9 */ - stl_p(p++, 0x3c0a0000 | (cm_base >> 16)); /* lui $10, cm_base >> 16 */ - if (is_64b) { - stl_p(p++, 0xfd0a0008); /* sd $10, 0x8($8) */ - } else { - stl_p(p++, 0xad0a0008); /* sw $10, 0x8($8) */ - } - stl_p(p++, 0x012a4025); /* or $8, $10 */ - - /* Move & enable GIC GCRs */ - stl_p(p++, 0x3c090000 | (gic_base >> 16)); /* lui $9, gic_base >> 16 */ - stl_p(p++, 0x35290001); /* ori $9, 0x1 */ - if (is_64b) { - stl_p(p++, 0xfd090080); /* sd $9, 0x80($8) */ - } else { - stl_p(p++, 0xad090080); /* sw $9, 0x80($8) */ - } - - /* Move & enable CPC GCRs */ - stl_p(p++, 0x3c090000 | (cpc_base >> 16)); /* lui $9, cpc_base >> 16 */ - stl_p(p++, 0x35290001); /* ori $9, 0x1 */ - if (is_64b) { - stl_p(p++, 0xfd090088); /* sd $9, 0x88($8) */ - } else { - stl_p(p++, 0xad090088); /* sw $9, 0x88($8) */ - } - /* * Setup argument registers to follow the UHI boot protocol: *