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[PULL,20/26] hw/mips/malta: Rewrite CP0_MVPConf0 access using deposit()

Message ID 20201213201946.236123-21-f4bug@amsat.org
State New
Headers show
Series [PULL,01/26] MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org | expand

Commit Message

Philippe Mathieu-Daudé Dec. 13, 2020, 8:19 p.m. UTC 
PTC field has 8 bits, PVPE has 4. We plan to use the
"hw/registerfields.h" API with MIPS CPU definitions
(target/mips/cpu.h). Meanwhile we use magic 8 and 4.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-6-f4bug@amsat.org>
---
 hw/mips/malta.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)
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Patch

diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index f06cb90a44a..366f4fdfcde 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -24,6 +24,7 @@ 
 
 #include "qemu/osdep.h"
 #include "qemu/units.h"
+#include "qemu/bitops.h"
 #include "qemu-common.h"
 #include "qemu/datadir.h"
 #include "cpu.h"
@@ -1136,8 +1137,11 @@  static void malta_mips_config(MIPSCPU *cpu)
     CPUState *cs = CPU(cpu);
 
     if (ase_mt_available(env)) {
-        env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
-                         ((smp_cpus * cs->nr_threads - 1) << CP0MVPC0_PTC);
+        env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
+                                           CP0MVPC0_PTC, 8,
+                                           smp_cpus * cs->nr_threads - 1);
+        env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
+                                           CP0MVPC0_PVPE, 4, smp_cpus - 1);
     }
 }