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[PULL,18/26] target/mips: Do not initialize MT registers if MT ASE absent

Message ID 20201213201946.236123-19-f4bug@amsat.org
State New
Headers show
Series [PULL,01/26] MAINTAINERS: chenhc@lemote.com -> chenhuacai@kernel.org | expand

Commit Message

Philippe Mathieu-Daudé Dec. 13, 2020, 8:19 p.m. UTC 
Do not initialize MT-related config registers if the MT ASE
is not present. As some functions access the 'mvp' structure,
we still zero-allocate it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201204222622.2743175-4-f4bug@amsat.org>
---
 target/mips/translate_init.c.inc | 4 ++++
 1 file changed, 4 insertions(+)
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Patch

diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc
index 5a926bc6df3..f72fee3b40a 100644
--- a/target/mips/translate_init.c.inc
+++ b/target/mips/translate_init.c.inc
@@ -993,6 +993,10 @@  static void mvp_init(CPUMIPSState *env)
 {
     env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
 
+    if (!ase_mt_available(env)) {
+        return;
+    }
+
     /* MVPConf1 implemented, TLB sharable, no gating storage support,
        programmable cache partitioning implemented, number of allocatable
        and shareable TLB entries, MVP has allocatable TCs, 2 VPEs