Message ID | 20200901151823.29785-1-peter.maydell@linaro.org |
---|---|
State | New |
Headers | show |
On Tue, 1 Sep 2020 at 16:18, Peter Maydell <peter.maydell@linaro.org> wrote: > > Just my fp16 work, plus some small stuff for the sbsa-ref board; > but my rule of thumb is to send a pullreq once I get over about > 30 patches... > > -- PMM > > The following changes since commit 2f4c51c0f384d7888a04b4815861e6d5fd244d75: > > Merge remote-tracking branch 'remotes/kraxel/tags/usb-20200831-pull-request' into staging (2020-08-31 19:39:13 +0100) > > are available in the Git repository at: > > https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200901 > > for you to fetch changes up to 3f462bf0f6ea6382dd1502d4eb1fcd33c8e774f5: > > hw/arm/sbsa-ref : Add embedded controller in secure memory (2020-09-01 14:01:34 +0100) > > ---------------------------------------------------------------- > target-arm queue: > * Implement fp16 support for AArch32 VFP and Neon > * hw/arm/sbsa-ref: add "reg" property to DT cpu nodes > * hw/arm/sbsa-ref : Add embedded controller in secure memory > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2 for any user-visible changes. -- PMM
Patchew URL: https://patchew.org/QEMU/20200901151823.29785-1-peter.maydell@linaro.org/ Hi, This series seems to have some coding style problems. See output below for more information: Type: series Message-id: 20200901151823.29785-1-peter.maydell@linaro.org Subject: [PULL 00/47] target-arm queue === TEST SCRIPT BEGIN === #!/bin/bash git rev-parse base > /dev/null || exit 0 git config --local diff.renamelimit 0 git config --local diff.renames True git config --local diff.algorithm histogram ./scripts/checkpatch.pl --mailback base.. === TEST SCRIPT END === Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384 From https://github.com/patchew-project/qemu * [new tag] patchew/159903454714.28509.7439453309116734374.stgit@pasha-ThinkPad-X280 -> patchew/159903454714.28509.7439453309116734374.stgit@pasha-ThinkPad-X280 - [tag update] patchew/20200828104102.4490-1-ahmedkhaledkaraman@gmail.com -> patchew/20200828104102.4490-1-ahmedkhaledkaraman@gmail.com - [tag update] patchew/20200901101951.85892-1-f4bug@amsat.org -> patchew/20200901101951.85892-1-f4bug@amsat.org - [tag update] patchew/20200901143424.884735-1-mreitz@redhat.com -> patchew/20200901143424.884735-1-mreitz@redhat.com - [tag update] patchew/20200902080552.159806-1-philmd@redhat.com -> patchew/20200902080552.159806-1-philmd@redhat.com * [new tag] patchew/20200902080801.160652-1-philmd@redhat.com -> patchew/20200902080801.160652-1-philmd@redhat.com * [new tag] patchew/20200902080909.161034-1-philmd@redhat.com -> patchew/20200902080909.161034-1-philmd@redhat.com * [new tag] patchew/20200902081445.3291-1-kraxel@redhat.com -> patchew/20200902081445.3291-1-kraxel@redhat.com Switched to a new branch 'test' 867f12e hw/arm/sbsa-ref : Add embedded controller in secure memory ef9b9cb hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref 845f48a hw/arm/sbsa-ref: add "reg" property to DT cpu nodes 3cac290 target/arm: Enable FP16 in '-cpu max' 7ac1305 target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS 8e7d9e3 target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations 2fb3424 target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations db719f9 target/arm: Implement fp16 for Neon VRINTX 07d6f02 target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode 0480984 target/arm: Implement fp16 for Neon VCVT with rounding modes 6fa11fb target/arm: Implement fp16 for Neon VCVT fixed-point 9a7522a target/arm: Convert Neon VCVT fixed-point to gvec dff0402 target/arm: Implement fp16 for Neon float-integer VCVT 78bda89 target/arm: Implement fp16 for Neon pairwise fp ops 7cc318e target/arm: Implement fp16 for Neon VRSQRTS 5662f40 target/arm: Implement fp16 for Neon VRECPS 943b926 target/arm: Implement fp16 for Neon fp compare-vs-0 3a0d121 target/arm: Implement fp16 for Neon VFMA, VMFS ff5b42c target/arm: Implement fp16 for Neon VMLA, VMLS operations a6112ba target/arm: Implement fp16 for Neon VMAXNM, VMINNM d2e6add target/arm: Implement fp16 for Neon VMAX, VMIN db83f64 target/arm: Implement fp16 for VACGE, VACGT ae8a9f3 target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons 6383a67 target/arm: Implement fp16 for Neon VABS, VNEG of floats aa9fecc target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec ccc9e6e target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL fe782c1 target/arm: Implement VFP fp16 VMOV between gp and halfprec registers 77ca57c target/arm: Implement new VFP fp16 insn VMOVX 92aba48 target/arm: Implement new VFP fp16 insn VINS ee2de45 target/arm: Implement VFP fp16 VRINT* 3c18e85 target/arm: Implement VFP fp16 VSEL 06590c3 target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode bc421d5 target/arm: Implement VFP fp16 VCVT between float and fixed-point ad1cb81 target/arm: Use macros instead of open-coding fp16 conversion helpers 93f7d9e target/arm: Make VFP_CONV_FIX macros take separate float type and float size 9c34df8 target/arm: Implement VFP fp16 VCVT between float and integer 32431b7 target/arm: Implement VFP fp16 VLDR and VSTR 9e7ad8d target/arm: Implement VFP fp16 VCMP 219e5e7 target/arm: Implement VFP fp16 for VMOV immediate 16625ab target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT af78af0 target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp() 790c683 target/arm: Implement VFP fp16 for fused-multiply-add 03011ed target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS 9e8666f target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL dc07ef0 target/arm: Implement VFP fp16 for VFP_BINOP operations eac3fc0 target/arm: Use correct ID register check for aa32_fp16_arith 348acc9 target/arm: Remove local definitions of float constants === OUTPUT BEGIN === 1/47 Checking commit 348acc9c588e (target/arm: Remove local definitions of float constants) 2/47 Checking commit eac3fc0b8d32 (target/arm: Use correct ID register check for aa32_fp16_arith) 3/47 Checking commit dc07ef09a498 (target/arm: Implement VFP fp16 for VFP_BINOP operations) 4/47 Checking commit 9e8666fb22d5 (target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL) 5/47 Checking commit 03011edc6f85 (target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS) 6/47 Checking commit 790c683d654e (target/arm: Implement VFP fp16 for fused-multiply-add) 7/47 Checking commit af78af05a66b (target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()) 8/47 Checking commit 16625abc0569 (target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT) 9/47 Checking commit 219e5e7476f1 (target/arm: Implement VFP fp16 for VMOV immediate) 10/47 Checking commit 9e7ad8d1257d (target/arm: Implement VFP fp16 VCMP) 11/47 Checking commit 32431b7da0e4 (target/arm: Implement VFP fp16 VLDR and VSTR) 12/47 Checking commit 9c34df8c2e06 (target/arm: Implement VFP fp16 VCVT between float and integer) 13/47 Checking commit 93f7d9e23b48 (target/arm: Make VFP_CONV_FIX macros take separate float type and float size) 14/47 Checking commit ad1cb81db5c7 (target/arm: Use macros instead of open-coding fp16 conversion helpers) 15/47 Checking commit bc421d53b796 (target/arm: Implement VFP fp16 VCVT between float and fixed-point) 16/47 Checking commit 06590c31de69 (target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode) 17/47 Checking commit 3c18e85bb42b (target/arm: Implement VFP fp16 VSEL) 18/47 Checking commit ee2de45ca5fa (target/arm: Implement VFP fp16 VRINT*) 19/47 Checking commit 92aba48130aa (target/arm: Implement new VFP fp16 insn VINS) 20/47 Checking commit 77ca57c7320f (target/arm: Implement new VFP fp16 insn VMOVX) 21/47 Checking commit fe782c1c0b07 (target/arm: Implement VFP fp16 VMOV between gp and halfprec registers) 22/47 Checking commit ccc9e6ea21bd (target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL) 23/47 Checking commit aa9feccae5df (target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec) 24/47 Checking commit 6383a67df0eb (target/arm: Implement fp16 for Neon VABS, VNEG of floats) 25/47 Checking commit ae8a9f353a29 (target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons) 26/47 Checking commit db83f645e754 (target/arm: Implement fp16 for VACGE, VACGT) 27/47 Checking commit d2e6add54fa2 (target/arm: Implement fp16 for Neon VMAX, VMIN) 28/47 Checking commit a6112ba7b02a (target/arm: Implement fp16 for Neon VMAXNM, VMINNM) WARNING: line over 80 characters #23: FILE: target/arm/helper.h:656: +DEF_HELPER_FLAGS_5(gvec_fmaxnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) WARNING: line over 80 characters #24: FILE: target/arm/helper.h:657: +DEF_HELPER_FLAGS_5(gvec_fmaxnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) WARNING: line over 80 characters #26: FILE: target/arm/helper.h:659: +DEF_HELPER_FLAGS_5(gvec_fminnum_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) WARNING: line over 80 characters #27: FILE: target/arm/helper.h:660: +DEF_HELPER_FLAGS_5(gvec_fminnum_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) total: 0 errors, 4 warnings, 67 lines checked Patch 28/47 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 29/47 Checking commit ff5b42c64d0f (target/arm: Implement fp16 for Neon VMLA, VMLS operations) 30/47 Checking commit 3a0d121aa9be (target/arm: Implement fp16 for Neon VFMA, VMFS) 31/47 Checking commit 943b926d0ee4 (target/arm: Implement fp16 for Neon fp compare-vs-0) 32/47 Checking commit 5662f407ddb0 (target/arm: Implement fp16 for Neon VRECPS) WARNING: line over 80 characters #35: FILE: target/arm/helper.h:676: +DEF_HELPER_FLAGS_5(gvec_recps_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) WARNING: line over 80 characters #36: FILE: target/arm/helper.h:677: +DEF_HELPER_FLAGS_5(gvec_recps_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) total: 0 errors, 2 warnings, 111 lines checked Patch 32/47 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 33/47 Checking commit 7cc318e9f3ec (target/arm: Implement fp16 for Neon VRSQRTS) WARNING: line over 80 characters #34: FILE: target/arm/helper.h:678: +DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) WARNING: line over 80 characters #35: FILE: target/arm/helper.h:679: +DEF_HELPER_FLAGS_5(gvec_rsqrts_nf_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) total: 0 errors, 2 warnings, 112 lines checked Patch 33/47 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 34/47 Checking commit 78bda89ed867 (target/arm: Implement fp16 for Neon pairwise fp ops) WARNING: Block comments use a leading /* on a separate line #128: FILE: target/arm/vec_helper.c:1785: + /* Read all inputs before writing outputs in case vm == vd */ \ WARNING: Block comments use a leading /* on a separate line #145: FILE: target/arm/vec_helper.c:1802: + /* Read all inputs before writing outputs in case vm == vd */ \ total: 0 errors, 2 warnings, 128 lines checked Patch 34/47 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 35/47 Checking commit dff0402b8387 (target/arm: Implement fp16 for Neon float-integer VCVT) 36/47 Checking commit 9a7522a1a77d (target/arm: Convert Neon VCVT fixed-point to gvec) 37/47 Checking commit 6fa11fb1670e (target/arm: Implement fp16 for Neon VCVT fixed-point) 38/47 Checking commit 04809847d926 (target/arm: Implement fp16 for Neon VCVT with rounding modes) 39/47 Checking commit 07d6f0234e79 (target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode) 40/47 Checking commit db719f9c7ab1 (target/arm: Implement fp16 for Neon VRINTX) 41/47 Checking commit 2fb34244e791 (target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations) 42/47 Checking commit 8e7d9e3ae492 (target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations) ERROR: space prohibited before that close parenthesis ')' #69: FILE: target/arm/vec_helper.c:1111: +DO_FMUL_IDX(gvec_fmul_idx_d, nop, float64, ) total: 1 errors, 0 warnings, 61 lines checked Patch 42/47 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 43/47 Checking commit 7ac1305e7585 (target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS) 44/47 Checking commit 3cac290bfc11 (target/arm: Enable FP16 in '-cpu max') 45/47 Checking commit 845f48ac9211 (hw/arm/sbsa-ref: add "reg" property to DT cpu nodes) 46/47 Checking commit ef9b9cbeaee6 (hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref) WARNING: added, moved or deleted file(s), does MAINTAINERS need updating? #34: new file mode 100644 total: 0 errors, 1 warnings, 103 lines checked Patch 46/47 has style problems, please review. If any of these errors are false positives report them to the maintainer, see CHECKPATCH in MAINTAINERS. 47/47 Checking commit 867f12e873f2 (hw/arm/sbsa-ref : Add embedded controller in secure memory) === OUTPUT END === Test command exited with code: 1 The full log is available at http://patchew.org/logs/20200901151823.29785-1-peter.maydell@linaro.org/testing.checkpatch/?type=message. --- Email generated automatically by Patchew [https://patchew.org/]. Please send your feedback to patchew-devel@redhat.com