diff mbox series

[2/3] target/riscv: Fix write_htinst() implementation

Message ID 20200729112801.108985-3-anup.patel@wdc.com
State New
Headers show
Series Trapped instruction encoding support | expand

Commit Message

Anup Patel July 29, 2020, 11:28 a.m. UTC 
The htinst CSR is writeable from M-mode and HS-mode so
we should not ignore writes to htinst CSR.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
 target/riscv/csr.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Alistair Francis Aug. 10, 2020, 10:37 p.m. UTC | #1 
On Wed, Jul 29, 2020 at 4:30 AM Anup Patel <anup.patel@wdc.com> wrote:
>
> The htinst CSR is writeable from M-mode and HS-mode so
> we should not ignore writes to htinst CSR.
>
> Signed-off-by: Anup Patel <anup.patel@wdc.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index f985b85de4..99fcb7f67d 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -943,6 +943,7 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
>
>  static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
>  {
> +    env->htinst = val;
>      return 0;
>  }
>
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f985b85de4..99fcb7f67d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -943,6 +943,7 @@  static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
 
 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
 {
+    env->htinst = val;
     return 0;
 }