Show patches with: Series = Trapped instruction encoding support       |    State = Action Required       |    Archived = No       |   3 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Trapped instruction encoding support - - - - --- 2020-07-29 Anup Patel New
[2/3] target/riscv: Fix write_htinst() implementation Trapped instruction encoding support - - 1 - --- 2020-07-29 Anup Patel New
[1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Trapped instruction encoding support - - 1 - --- 2020-07-29 Anup Patel New