[RFC,v2,01/76] target/riscv: drop vector 0.7.1 support

Message ID	20200722091641.8834-2-frank.chang@sifive.com
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v2 01/76] target/riscv: drop vector 0.7.1 support Date: Wed, 22 Jul 2020 17:15:24 +0800 Message-Id: <20200722091641.8834-2-frank.chang@sifive.com> In-Reply-To: <20200722091641.8834-1-frank.chang@sifive.com> References: <20200722091641.8834-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com Precedence: list Cc: Frank Chang <frank.chang@sifive.com>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@dabbelt.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/riscv: support vector extension v0.9 \| expand [RFC,v2,00/76] target/riscv: support vector extension v0.9 [RFC,v2,01/76] target/riscv: drop vector 0.7.1 support [RFC,v2,02/76] target/riscv: rvv-0.9: support vector 0.9 [RFC,v2,03/76] target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion [RFC,v2,04/76] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() [RFC,v2,05/76] target/riscv: fix return value of do_opivx_widen() [RFC,v2,06/76] target/riscv: fix vill bit index in vtype register [RFC,v2,07/76] target/riscv: Use FIELD_EX32() to extract wd field [RFC,v2,08/76] target/riscv: rvv-0.9: add mstatus VS field [RFC,v2,09/76] target/riscv: rvv-0.9: add sstatus VS field [RFC,v2,10/76] target/riscv: rvv-0.9: add translation-time vector context status [RFC,v2,11/76] target/riscv: rvv-0.9: remove vxrm and vxsat fields from fcsr register [RFC,v2,12/76] target/riscv: rvv-0.9: add vcsr register [RFC,v2,13/76] target/riscv: rvv-0.9: add vlenb register [RFC,v2,14/76] target/riscv: rvv-0.9: remove MLEN calculations [RFC,v2,15/76] target/riscv: rvv-0.9: add fractional LMUL [RFC,v2,16/76] target/riscv: rvv-0.9: add VMA and VTA [RFC,v2,17/76] target/riscv: rvv-0.9: update check functions [RFC,v2,18/76] target/riscv: introduce more imm value modes in translator functions [RFC,v2,19/76] target/riscv: rvv-0.9: add narrower_nanbox_fpr helper [RFC,v2,20/76] target/riscv: rvv-0.9: apply narrower nanbox helper in opfvf_trans [RFC,v2,21/76] target/riscv: rvv-0.9: configure instructions [RFC,v2,22/76] target/riscv: rvv-0.9: stride load and store instructions [RFC,v2,23/76] target/riscv: rvv-0.9: index load and store instructions [RFC,v2,24/76] target/riscv: rvv-0.9: fix address index overflow bug of indexed load/store insns [RFC,v2,25/76] target/riscv: rvv-0.9: fault-only-first unit stride load [RFC,v2,26/76] target/riscv: rvv-0.9: amo operations [RFC,v2,27/76] target/riscv: rvv-0.9: load/store whole register instructions [RFC,v2,28/76] target/riscv: rvv-0.9: update vext_max_elems() for load/store insns [RFC,v2,29/76] target/riscv: rvv-0.9: take fractional LMUL into vector max elements calculation [RFC,v2,30/76] target/riscv: rvv-0.9: floating-point square-root instruction [RFC,v2,31/76] target/riscv: rvv-0.9: floating-point classify instructions [RFC,v2,32/76] target/riscv: rvv-0.9: mask population count instruction [RFC,v2,33/76] target/riscv: rvv-0.9: find-first-set mask bit instruction [RFC,v2,34/76] target/riscv: rvv-0.9: set-X-first mask bit instructions [RFC,v2,35/76] target/riscv: rvv-0.9: iota instruction [RFC,v2,36/76] target/riscv: rvv-0.9: element index instruction [RFC,v2,37/76] target/riscv: rvv-0.9: allow load element with sign-extended [RFC,v2,38/76] target/riscv: rvv-0.9: register gather instructions [RFC,v2,39/76] target/riscv: rvv-0.9: integer scalar move instructions [RFC,v2,40/76] target/riscv: rvv-0.9: floating-point move instruction [RFC,v2,41/76] target/riscv: rvv-0.9: floating-point scalar move instructions [RFC,v2,42/76] target/riscv: rvv-0.9: whole register move instructions [RFC,v2,43/76] target/riscv: rvv-0.9: integer extension instructions [RFC,v2,44/76] target/riscv: rvv-0.9: single-width averaging add and subtract instructions [RFC,v2,45/76] target/riscv: rvv-0.9: single-width bit shift instructions [RFC,v2,46/76] target/riscv: rvv-0.9: integer add-with-carry/subtract-with-borrow [RFC,v2,47/76] target/riscv: rvv-0.9: narrowing integer right shift instructions [RFC,v2,48/76] target/riscv: rvv-0.9: widening integer multiply-add instructions [RFC,v2,49/76] target/riscv: rvv-0.9: quad-widening integer multiply-add instructions [RFC,v2,50/76] target/riscv: rvv-0.9: single-width saturating add and subtract instructions [RFC,v2,51/76] target/riscv: rvv-0.9: integer comparison instructions [RFC,v2,52/76] fpu: implement full set compare for fp16 [RFC,v2,53/76] target/riscv: use softfloat lib float16 comparison functions [RFC,v2,54/76] target/riscv: rvv-0.9: floating-point compare instructions [RFC,v2,55/76] target/riscv: rvv-0.9: single-width integer reduction instructions [RFC,v2,56/76] target/riscv: rvv-0.9: widening integer reduction instructions [RFC,v2,57/76] target/riscv: rvv-0.9: mask-register logical instructions [RFC,v2,58/76] target/riscv: rvv-0.9: slide instructions [RFC,v2,59/76] target/riscv: rvv-0.9: floating-point slide instructions [RFC,v2,60/76] target/riscv: rvv-0.9: narrowing fixed-point clip instructions [RFC,v2,61/76] target/riscv: rvv-0.9: floating-point/integer type-convert instructions [RFC,v2,62/76] target/riscv: rvv-0.9: single-width floating-point reduction [RFC,v2,63/76] target/riscv: rvv-0.9: widening floating-point reduction instructions [RFC,v2,64/76] target/riscv: rvv-0.9: single-width scaling shift instructions [RFC,v2,65/76] target/riscv: rvv-0.9: remove widening saturating scaled multiply-add [RFC,v2,66/76] target/riscv: rvv-0.9: remove vmford.vv and vmford.vf [RFC,v2,67/76] target/riscv: rvv-0.9: remove integer extract instruction [RFC,v2,68/76] fpu: add api to handle alternative sNaN propagation [RFC,v2,69/76] target/riscv: rvv-0.9: floating-point min/max instructions [RFC,v2,70/76] softfloat: add fp16 and uint8/int8 interconvert functions [RFC,v2,71/76] target/riscv: rvv-0.9: widening floating-point/integer type-convert [RFC,v2,72/76] target/riscv: rvv-0.9: narrowing floating-point/integer type-convert [RFC,v2,73/76] fpu: fix float16 nan check [RFC,v2,74/76] target/riscv: gdb: modify gdb csr xml file to align with csr register map [RFC,v2,75/76] target/riscv: gdb: support vector registers for rv64 [RFC,v2,76/76] target/riscv: gdb: support vector registers for rv32

Frank Chang July 22, 2020, 9:15 a.m. UTC

From: Frank Chang <frank.chang@sifive.com>

Signed-off-by: Frank Chang <frank.chang@sifive.com>
---
 target/riscv/cpu.c | 24 ++++++------------------
 target/riscv/cpu.h |  2 --
 2 files changed, 6 insertions(+), 20 deletions(-)

Alistair Francis July 22, 2020, 4:37 p.m. UTC | #1

On Wed, Jul 22, 2020 at 2:18 AM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 24 ++++++------------------
>  target/riscv/cpu.h |  2 --
>  2 files changed, 6 insertions(+), 20 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 228b9bdb5d..2800953e6c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -106,11 +106,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
>      env->priv_ver = priv_ver;
>  }
>
> -static void set_vext_version(CPURISCVState *env, int vext_ver)
> -{
> -    env->vext_ver = vext_ver;
> -}
> -
>  static void set_feature(CPURISCVState *env, int feature)
>  {
>      env->features |= (1ULL << feature);
> @@ -339,7 +334,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>      CPURISCVState *env = &cpu->env;
>      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>      int priv_version = PRIV_VERSION_1_11_0;
> -    int vext_version = VEXT_VERSION_0_07_1;
>      target_ulong target_misa = 0;
>      Error *local_err = NULL;
>
> @@ -363,7 +357,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>      }
>
>      set_priv_version(env, priv_version);
> -    set_vext_version(env, vext_version);
>
>      if (cpu->cfg.mmu) {
>          set_feature(env, RISCV_FEATURE_MMU);
> @@ -455,19 +448,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>                  return;
>              }
>              if (cpu->cfg.vext_spec) {
> -                if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
> -                    vext_version = VEXT_VERSION_0_07_1;
> -                } else {
> -                    error_setg(errp,
> -                           "Unsupported vector spec version '%s'",
> -                           cpu->cfg.vext_spec);
> -                    return;
> -                }
> +                error_setg(errp,
> +                       "Unsupported vector spec version '%s'",
> +                       cpu->cfg.vext_spec);
> +                return;
>              } else {
> -                qemu_log("vector verison is not specified, "
> -                        "use the default value v0.7.1\n");
> +                qemu_log("vector version is not specified\n");
> +                return;
>              }
> -            set_vext_version(env, vext_version);
>          }
>
>          set_misa(env, RVXLEN | target_misa);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index eef20ca6e5..6766dcd914 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -79,8 +79,6 @@ enum {
>  #define PRIV_VERSION_1_10_0 0x00011000
>  #define PRIV_VERSION_1_11_0 0x00011100
>
> -#define VEXT_VERSION_0_07_1 0x00000701
> -
>  #define TRANSLATE_PMP_FAIL 2
>  #define TRANSLATE_FAIL 1
>  #define TRANSLATE_SUCCESS 0
> --
> 2.17.1
>
>

Palmer Dabbelt July 27, 2020, 7:54 p.m. UTC | #2

On Wed, 22 Jul 2020 02:15:24 PDT (-0700), frank.chang@sifive.com wrote:
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> ---
>  target/riscv/cpu.c | 24 ++++++------------------
>  target/riscv/cpu.h |  2 --
>  2 files changed, 6 insertions(+), 20 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 228b9bdb5d..2800953e6c 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -106,11 +106,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
>      env->priv_ver = priv_ver;
>  }
>
> -static void set_vext_version(CPURISCVState *env, int vext_ver)
> -{
> -    env->vext_ver = vext_ver;
> -}
> -
>  static void set_feature(CPURISCVState *env, int feature)
>  {
>      env->features |= (1ULL << feature);
> @@ -339,7 +334,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>      CPURISCVState *env = &cpu->env;
>      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
>      int priv_version = PRIV_VERSION_1_11_0;
> -    int vext_version = VEXT_VERSION_0_07_1;
>      target_ulong target_misa = 0;
>      Error *local_err = NULL;
>
> @@ -363,7 +357,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>      }
>
>      set_priv_version(env, priv_version);
> -    set_vext_version(env, vext_version);
>
>      if (cpu->cfg.mmu) {
>          set_feature(env, RISCV_FEATURE_MMU);
> @@ -455,19 +448,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
>                  return;
>              }
>              if (cpu->cfg.vext_spec) {
> -                if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
> -                    vext_version = VEXT_VERSION_0_07_1;
> -                } else {
> -                    error_setg(errp,
> -                           "Unsupported vector spec version '%s'",
> -                           cpu->cfg.vext_spec);
> -                    return;
> -                }
> +                error_setg(errp,
> +                       "Unsupported vector spec version '%s'",
> +                       cpu->cfg.vext_spec);
> +                return;
>              } else {
> -                qemu_log("vector verison is not specified, "
> -                        "use the default value v0.7.1\n");
> +                qemu_log("vector version is not specified\n");
> +                return;
>              }
> -            set_vext_version(env, vext_version);
>          }
>
>          set_misa(env, RVXLEN | target_misa);
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index eef20ca6e5..6766dcd914 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -79,8 +79,6 @@ enum {
>  #define PRIV_VERSION_1_10_0 0x00011000
>  #define PRIV_VERSION_1_11_0 0x00011100
>
> -#define VEXT_VERSION_0_07_1 0x00000701
> -
>  #define TRANSLATE_PMP_FAIL 2
>  #define TRANSLATE_FAIL 1
>  #define TRANSLATE_SUCCESS 0

If I'm reading things correctly, 5.0 did not have the V extension.  This means
that we can technically drop 0.7.1 from QEMU, as it's never been released.
That said, I'd still prefer to avoid dropping 0.7.1 so late in the release
cycle (it's already soft freeze, right?).  Given the extended length of the V
extension development process it seems likely that 0.7.1 is going to end up in
some silicon, which means it would be quite useful to have it in QEMU.

I understand it's a lot more work to maintain multiple vector extensions, but
it was very useful to have multiple privileged extensions supported in QEMU
while that was all getting sorted out and as the vector drafts has massive
differences it'll probably be even more useful.

Alistair Francis July 27, 2020, 7:55 p.m. UTC | #3

On Mon, Jul 27, 2020 at 12:54 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Wed, 22 Jul 2020 02:15:24 PDT (-0700), frank.chang@sifive.com wrote:
> > From: Frank Chang <frank.chang@sifive.com>
> >
> > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > ---
> >  target/riscv/cpu.c | 24 ++++++------------------
> >  target/riscv/cpu.h |  2 --
> >  2 files changed, 6 insertions(+), 20 deletions(-)
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 228b9bdb5d..2800953e6c 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -106,11 +106,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver)
> >      env->priv_ver = priv_ver;
> >  }
> >
> > -static void set_vext_version(CPURISCVState *env, int vext_ver)
> > -{
> > -    env->vext_ver = vext_ver;
> > -}
> > -
> >  static void set_feature(CPURISCVState *env, int feature)
> >  {
> >      env->features |= (1ULL << feature);
> > @@ -339,7 +334,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >      CPURISCVState *env = &cpu->env;
> >      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> >      int priv_version = PRIV_VERSION_1_11_0;
> > -    int vext_version = VEXT_VERSION_0_07_1;
> >      target_ulong target_misa = 0;
> >      Error *local_err = NULL;
> >
> > @@ -363,7 +357,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >      }
> >
> >      set_priv_version(env, priv_version);
> > -    set_vext_version(env, vext_version);
> >
> >      if (cpu->cfg.mmu) {
> >          set_feature(env, RISCV_FEATURE_MMU);
> > @@ -455,19 +448,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
> >                  return;
> >              }
> >              if (cpu->cfg.vext_spec) {
> > -                if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
> > -                    vext_version = VEXT_VERSION_0_07_1;
> > -                } else {
> > -                    error_setg(errp,
> > -                           "Unsupported vector spec version '%s'",
> > -                           cpu->cfg.vext_spec);
> > -                    return;
> > -                }
> > +                error_setg(errp,
> > +                       "Unsupported vector spec version '%s'",
> > +                       cpu->cfg.vext_spec);
> > +                return;
> >              } else {
> > -                qemu_log("vector verison is not specified, "
> > -                        "use the default value v0.7.1\n");
> > +                qemu_log("vector version is not specified\n");
> > +                return;
> >              }
> > -            set_vext_version(env, vext_version);
> >          }
> >
> >          set_misa(env, RVXLEN | target_misa);
> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > index eef20ca6e5..6766dcd914 100644
> > --- a/target/riscv/cpu.h
> > +++ b/target/riscv/cpu.h
> > @@ -79,8 +79,6 @@ enum {
> >  #define PRIV_VERSION_1_10_0 0x00011000
> >  #define PRIV_VERSION_1_11_0 0x00011100
> >
> > -#define VEXT_VERSION_0_07_1 0x00000701
> > -
> >  #define TRANSLATE_PMP_FAIL 2
> >  #define TRANSLATE_FAIL 1
> >  #define TRANSLATE_SUCCESS 0
>
> If I'm reading things correctly, 5.0 did not have the V extension.  This means
> that we can technically drop 0.7.1 from QEMU, as it's never been released.

There is no intention of this making it into 5.1. We are currently in
hard freeze.

The idea is that QEMU 5.1 will support v0.7.1 and then hopefully 5.2
will support v0.9.

> That said, I'd still prefer to avoid dropping 0.7.1 so late in the release
> cycle (it's already soft freeze, right?).  Given the extended length of the V
> extension development process it seems likely that 0.7.1 is going to end up in
> some silicon, which means it would be quite useful to have it in QEMU.

Agreed!

>
> I understand it's a lot more work to maintain multiple vector extensions, but
> it was very useful to have multiple privileged extensions supported in QEMU
> while that was all getting sorted out and as the vector drafts has massive
> differences it'll probably be even more useful.

Hopefully a release will be enough for this as managing both will be a
huge maintenance burden.

Alistair

>

Frank Chang July 30, 2020, 8:07 a.m. UTC | #4

On Tue, Jul 28, 2020 at 4:05 AM Alistair Francis <alistair23@gmail.com>
wrote:

> On Mon, Jul 27, 2020 at 12:54 PM Palmer Dabbelt <palmer@dabbelt.com>
> wrote:
> >
> > On Wed, 22 Jul 2020 02:15:24 PDT (-0700), frank.chang@sifive.com wrote:
> > > From: Frank Chang <frank.chang@sifive.com>
> > >
> > > Signed-off-by: Frank Chang <frank.chang@sifive.com>
> > > ---
> > >  target/riscv/cpu.c | 24 ++++++------------------
> > >  target/riscv/cpu.h |  2 --
> > >  2 files changed, 6 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > index 228b9bdb5d..2800953e6c 100644
> > > --- a/target/riscv/cpu.c
> > > +++ b/target/riscv/cpu.c
> > > @@ -106,11 +106,6 @@ static void set_priv_version(CPURISCVState *env,
> int priv_ver)
> > >      env->priv_ver = priv_ver;
> > >  }
> > >
> > > -static void set_vext_version(CPURISCVState *env, int vext_ver)
> > > -{
> > > -    env->vext_ver = vext_ver;
> > > -}
> > > -
> > >  static void set_feature(CPURISCVState *env, int feature)
> > >  {
> > >      env->features |= (1ULL << feature);
> > > @@ -339,7 +334,6 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> > >      CPURISCVState *env = &cpu->env;
> > >      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> > >      int priv_version = PRIV_VERSION_1_11_0;
> > > -    int vext_version = VEXT_VERSION_0_07_1;
> > >      target_ulong target_misa = 0;
> > >      Error *local_err = NULL;
> > >
> > > @@ -363,7 +357,6 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> > >      }
> > >
> > >      set_priv_version(env, priv_version);
> > > -    set_vext_version(env, vext_version);
> > >
> > >      if (cpu->cfg.mmu) {
> > >          set_feature(env, RISCV_FEATURE_MMU);
> > > @@ -455,19 +448,14 @@ static void riscv_cpu_realize(DeviceState *dev,
> Error **errp)
> > >                  return;
> > >              }
> > >              if (cpu->cfg.vext_spec) {
> > > -                if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) {
> > > -                    vext_version = VEXT_VERSION_0_07_1;
> > > -                } else {
> > > -                    error_setg(errp,
> > > -                           "Unsupported vector spec version '%s'",
> > > -                           cpu->cfg.vext_spec);
> > > -                    return;
> > > -                }
> > > +                error_setg(errp,
> > > +                       "Unsupported vector spec version '%s'",
> > > +                       cpu->cfg.vext_spec);
> > > +                return;
> > >              } else {
> > > -                qemu_log("vector verison is not specified, "
> > > -                        "use the default value v0.7.1\n");
> > > +                qemu_log("vector version is not specified\n");
> > > +                return;
> > >              }
> > > -            set_vext_version(env, vext_version);
> > >          }
> > >
> > >          set_misa(env, RVXLEN | target_misa);
> > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> > > index eef20ca6e5..6766dcd914 100644
> > > --- a/target/riscv/cpu.h
> > > +++ b/target/riscv/cpu.h
> > > @@ -79,8 +79,6 @@ enum {
> > >  #define PRIV_VERSION_1_10_0 0x00011000
> > >  #define PRIV_VERSION_1_11_0 0x00011100
> > >
> > > -#define VEXT_VERSION_0_07_1 0x00000701
> > > -
> > >  #define TRANSLATE_PMP_FAIL 2
> > >  #define TRANSLATE_FAIL 1
> > >  #define TRANSLATE_SUCCESS 0
> >
> > If I'm reading things correctly, 5.0 did not have the V extension.  This
> means
> > that we can technically drop 0.7.1 from QEMU, as it's never been
> released.
>
> There is no intention of this making it into 5.1. We are currently in
> hard freeze.
>
> The idea is that QEMU 5.1 will support v0.7.1 and then hopefully 5.2
> will support v0.9.
>
> > That said, I'd still prefer to avoid dropping 0.7.1 so late in the
> release
> > cycle (it's already soft freeze, right?).  Given the extended length of
> the V
> > extension development process it seems likely that 0.7.1 is going to end
> up in
> > some silicon, which means it would be quite useful to have it in QEMU.
>
> Agreed!
>
> >
> > I understand it's a lot more work to maintain multiple vector
> extensions, but
> > it was very useful to have multiple privileged extensions supported in
> QEMU
> > while that was all getting sorted out and as the vector drafts has
> massive
> > differences it'll probably be even more useful.
>
> Hopefully a release will be enough for this as managing both will be a
> huge maintenance burden.
>
> Alistair
>
> >




Although RVV v1.0 spec is not ratified yet.
However, the differences between RVV v0.9 by far are minor:
1. SLEN=VLEN layout mandatory.
>> Luckily we haven't defined *slen* in our RVV implementation by far, so
we can just ignore the change.
2. Support ELEN > VLEN for LMUL > 1
3. Defined vector FP exception behavior.
4. Added reciprocal and reciprocal square-root estimate instructions.
>> *vfrece7.v* and *vfrsqrte7.v* instructions are added, but the
behaviors are still undefined.
5. Defined hint behavior on whole register moves and load/stores to enable
microarchitectures with internal data rearrangement.
>> Serveral *vl**<NF>re<EEW>.v* and *vs<NF>r.v* instructions are added.
6. Added *vrgatherei16* instruction.
7. Rearranged bits in *vtype* to make *vlmul* bits into a contiguous field.

As QEMU v5.1 is already hard-freezed and should be released between
2020/08/11 and 2020/08/18.
So perhaps we still have some time for waiting RVV v1.0 spec. to be
ratified before QEMU v5.2 is soft-freezed?

We have already made these RVV v1.0 changes in our local branch.
(*vfrece7.v* and *vfrsqrte7.v* instructions are not included as they're not
defined yet.)
So, if it's okay, we can skip RVV v0.9 and bump to RVV v1.0 directly in our
next version of patchset.
Which I think may relieve the burden for the community to maintain
multi-version of vector drafts.

Any thoughts?

Frank Chang

Richard Henderson July 30, 2020, 12:27 p.m. UTC | #5

On 7/30/20 1:07 AM, Frank Chang wrote:
> So, if it's okay, we can skip RVV v0.9 and bump to RVV v1.0 directly in our
> next version of patchset.
> Which I think may relieve the burden for the community to maintain
> multi-version of vector drafts.

That would be my preference.  Thanks,


r~

[RFC,v2,01/76] target/riscv: drop vector 0.7.1 support

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