| Message ID | 20200701183949.398134-5-atish.patra@wdc.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v4,1/4] riscv: Unify Qemu's reset vector code path | expand |
On Thu, Jul 2, 2020 at 2:39 AM Atish Patra <atish.patra@wdc.com> wrote: > > Even though the start address in ROM code is declared as a 64 bit address > for RV64, it can't be used as upper bits are set to zero in ROM code. > > Update the ROM code correctly to reflect the 64bit value. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > hw/riscv/boot.c | 6 +++++- > hw/riscv/sifive_u.c | 6 +++++- > 2 files changed, 10 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
On Wed, Jul 1, 2020 at 11:40 AM Atish Patra <atish.patra@wdc.com> wrote: > > Even though the start address in ROM code is declared as a 64 bit address > for RV64, it can't be used as upper bits are set to zero in ROM code. > > Update the ROM code correctly to reflect the 64bit value. > > Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > hw/riscv/boot.c | 6 +++++- > hw/riscv/sifive_u.c | 6 +++++- > 2 files changed, 10 insertions(+), 2 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index feff6e3f4ed5..4c6c101ff179 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, > uint32_t fdt_load_addr, void *fdt) > { > int i; > + uint32_t start_addr_hi32 = 0x00000000; > > + #if defined(TARGET_RISCV64) > + start_addr_hi32 = start_addr >> 32; > + #endif > /* reset vector */ > uint32_t reset_vec[10] = { > 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ > @@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, > #endif > 0x00028067, /* jr t0 */ > start_addr, /* start: .dword */ > - 0x00000000, > + start_addr_hi32, > fdt_load_addr, /* fdt_laddr: .dword */ > 0x00000000, > /* fw_dyn: */ > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 901efab9d5bd..3aaee82f1f28 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine) > MemoryRegion *main_mem = g_new(MemoryRegion, 1); > MemoryRegion *flash0 = g_new(MemoryRegion, 1); > target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; > + uint32_t start_addr_hi32 = 0x00000000; > int i; > uint32_t fdt_load_addr; > uint64_t kernel_entry; > @@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine) > /* Compute the fdt load address in dram */ > fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, > machine->ram_size, s->fdt); > + #if defined(TARGET_RISCV64) > + start_addr_hi32 = start_addr >> 32; > + #endif > > /* reset vector */ > uint32_t reset_vec[11] = { > @@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine) > #endif > 0x00028067, /* jr t0 */ > start_addr, /* start: .dword */ > - 0x00000000, > + start_addr_hi32, > fdt_load_addr, /* fdt_laddr: .dword */ > 0x00000000, > /* fw_dyn: */ > -- > 2.26.2 > >
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index feff6e3f4ed5..4c6c101ff179 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -226,7 +226,11 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, uint32_t fdt_load_addr, void *fdt) { int i; + uint32_t start_addr_hi32 = 0x00000000; + #if defined(TARGET_RISCV64) + start_addr_hi32 = start_addr >> 32; + #endif /* reset vector */ uint32_t reset_vec[10] = { 0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */ @@ -241,7 +245,7 @@ void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, #endif 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ - 0x00000000, + start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, /* fw_dyn: */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 901efab9d5bd..3aaee82f1f28 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -378,6 +378,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *flash0 = g_new(MemoryRegion, 1); target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; + uint32_t start_addr_hi32 = 0x00000000; int i; uint32_t fdt_load_addr; uint64_t kernel_entry; @@ -460,6 +461,9 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, machine->ram_size, s->fdt); + #if defined(TARGET_RISCV64) + start_addr_hi32 = start_addr >> 32; + #endif /* reset vector */ uint32_t reset_vec[11] = { @@ -476,7 +480,7 @@ static void sifive_u_machine_init(MachineState *machine) #endif 0x00028067, /* jr t0 */ start_addr, /* start: .dword */ - 0x00000000, + start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ 0x00000000, /* fw_dyn: */
Even though the start address in ROM code is declared as a 64 bit address for RV64, it can't be used as upper bits are set to zero in ROM code. Update the ROM code correctly to reflect the 64bit value. Signed-off-by: Atish Patra <atish.patra@wdc.com> --- hw/riscv/boot.c | 6 +++++- hw/riscv/sifive_u.c | 6 +++++- 2 files changed, 10 insertions(+), 2 deletions(-)