[PULL,13/13] target/openrisc: Update cpu "any" to v1.3

Message ID	20190904204507.32457-14-richard.henderson@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Date: Wed, 4 Sep 2019 13:45:07 -0700 Message-Id: <20190904204507.32457-14-richard.henderson@linaro.org> In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org> References: <20190904204507.32457-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PULL 13/13] target/openrisc: Update cpu "any" to v1.3 Precedence: list Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write \| expand [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write [PULL,02/13] target/openrisc: Replace cpu register array with a function [PULL,03/13] target/openrisc: Cache R0 in DisasContext [PULL,04/13] target/openrisc: Make VR and PPC read-only [PULL,05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init [PULL,06/13] target/openrisc: Add VR2 and AVR special processor registers [PULL,07/13] target/openrisc: Fix lf.ftoi.s [PULL,08/13] target/openrisc: Check CPUCFG_OF32S for float insns [PULL,09/13] target/openrisc: Add support for ORFPX64A32 [PULL,10/13] target/openrisc: Implement unordered fp comparisons [PULL,11/13] target/openrisc: Implement move to/from FPCSR [PULL,12/13] target/openrisc: Implement l.adrp [PULL,13/13] target/openrisc: Update cpu "any" to v1.3

Message ID

20190904204507.32457-14-richard.henderson@linaro.org

State

New

Headers

From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Date: Wed,  4 Sep 2019 13:45:07 -0700
Message-Id: <20190904204507.32457-14-richard.henderson@linaro.org>
In-Reply-To: <20190904204507.32457-1-richard.henderson@linaro.org>
References: <20190904204507.32457-1-richard.henderson@linaro.org>
Subject: [Qemu-devel] [PULL 13/13] target/openrisc: Update cpu "any" to v1.3
Precedence: list
Cc: peter.maydell@linaro.org
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
Sender: "Qemu-devel"
	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write | expand

Commit Message

Richard Henderson Sept. 4, 2019, 8:45 p.m. UTC

Now that the two updates from v1.3 are implemented,
update the "any" cpu to enable it.

Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/openrisc/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index f96a69e278..506aec6bfb 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -129,7 +129,7 @@  static void openrisc_any_initfn(Object *obj)
 
     cpu->env.vr = 0x13000040;   /* Obsolete VER + UVRP for new SPRs */
     cpu->env.vr2 = 0;           /* No version specific id */
-    cpu->env.avr = 0x01010000;  /* Architecture v1.1 */
+    cpu->env.avr = 0x01030000;  /* Architecture v1.3 */
 
     cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP;
     cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S |

[PULL,13/13] target/openrisc: Update cpu "any" to v1.3

Commit Message

Patch