Show patches with: Series = [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write       |    State = Action Required       |    Archived = No       |   13 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[PULL,13/13] target/openrisc: Update cpu "any" to v1.3 [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,12/13] target/openrisc: Implement l.adrp [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,11/13] target/openrisc: Implement move to/from FPCSR [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,10/13] target/openrisc: Implement unordered fp comparisons [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,09/13] target/openrisc: Add support for ORFPX64A32 [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,08/13] target/openrisc: Check CPUCFG_OF32S for float insns [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,07/13] target/openrisc: Fix lf.ftoi.s [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,06/13] target/openrisc: Add VR2 and AVR special processor registers [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - - - --- 2019-09-04 Richard Henderson New
[PULL,05/13] target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,04/13] target/openrisc: Make VR and PPC read-only [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,03/13] target/openrisc: Cache R0 in DisasContext [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,02/13] target/openrisc: Replace cpu register array with a function [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New
[PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write [PULL,01/13] target/openrisc: Add DisasContext parameter to check_r0_write - - 1 - --- 2019-09-04 Richard Henderson New