diff mbox series

[04/42] target/arm: Fix Cortex-R5F MVFR values

Message ID	20190606174609.20487-5-peter.maydell@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Peter Maydell <peter.maydell@linaro.org> To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 6 Jun 2019 18:45:31 +0100 Message-Id: <20190606174609.20487-5-peter.maydell@linaro.org> In-Reply-To: <20190606174609.20487-1-peter.maydell@linaro.org> References: <20190606174609.20487-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH 04/42] target/arm: Fix Cortex-R5F MVFR values Precedence: list Cc: Richard Henderson <richard.henderson@linaro.org> Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/arm: Convert VFP decoder to decodetree \| expand [00/42] target/arm: Convert VFP decoder to decodetree [01/42] decodetree: Fix comparison of Field [02/42] target/arm: Add stubs for AArch32 VFP decodetree [03/42] target/arm: Factor out VFP access checking code [04/42] target/arm: Fix Cortex-R5F MVFR values [05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max [06/42] target/arm: Convert the VSEL instructions to decodetree [07/42] target/arm: Convert VMINNM, VMAXNM to decodetree [08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree [09/42] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree [10/42] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c [11/42] target/arm: Add helpers for VFP register loads and stores [12/42] target/arm: Convert "double-precision" register moves to decodetree [13/42] target/arm: Convert "single-precision" register moves to decodetree [14/42] target/arm: Convert VFP two-register transfer insns to decodetree [15/42] target/arm: Convert VFP VLDR and VSTR to decodetree [16/42] target/arm: Convert the VFP load/store multiple insns to decodetree [17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d [18/42] target/arm: Convert VFP VMLA to decodetree [19/42] target/arm: Convert VFP VMLS to decodetree [20/42] target/arm: Convert VFP VNMLS to decodetree [21/42] target/arm: Convert VFP VNMLA to decodetree [22/42] target/arm: Convert VMUL to decodetree [23/42] target/arm: Convert VNMUL to decodetree [24/42] target/arm: Convert VADD to decodetree [25/42] target/arm: Convert VSUB to decodetree [26/42] target/arm: Convert VDIV to decodetree [27/42] target/arm: Convert VFP fused multiply-add insns to decodetree [28/42] target/arm: Convert VMOV (imm) to decodetree [29/42] target/arm: Convert VABS to decodetree [30/42] target/arm: Convert VNEG to decodetree [31/42] target/arm: Convert VSQRT to decodetree [32/42] target/arm: Convert VMOV (register) to decodetree [33/42] target/arm: Convert VFP comparison insns to decodetree [34/42] target/arm: Convert the VCVT-from-f16 insns to decodetree [35/42] target/arm: Convert the VCVT-to-f16 insns to decodetree [36/42] target/arm: Convert VFP round insns to decodetree [37/42] target/arm: Convert double-single precision conversion insns to decodetree [38/42] target/arm: Convert integer-to-float insns to decodetree [39/42] target/arm: Convert VJCVT to decodetree [40/42] target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree [41/42] target/arm: Convert float-to-integer VCVT insns to decodetree [42/42] target/arm: Fix short-vector increment behaviour

Commit Message

Peter Maydell June 6, 2019, 5:45 p.m. UTC

The Cortex-R5F initfn was not correctly setting up the MVFR
ID register values. Fill these in, since some subsequent patches
will use ID register checks rather than CPU feature bit checks.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Richard Henderson June 7, 2019, 2:50 p.m. UTC | #1

On 6/6/19 12:45 PM, Peter Maydell wrote:
> The Cortex-R5F initfn was not correctly setting up the MVFR
> ID register values. Fill these in, since some subsequent patches
> will use ID register checks rather than CPU feature bit checks.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/arm/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


r~

diff mbox series

Patch

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 9b23ac2c935..044c4dd738b 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1608,6 +1608,8 @@  static void cortex_r5f_initfn(Object *obj)
 
     cortex_r5_initfn(obj);
     set_feature(&cpu->env, ARM_FEATURE_VFP3);
+    cpu->isar.mvfr0 = 0x10110221;
+    cpu->isar.mvfr1 = 0x00000011;
 }
 
 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {