diff mbox series

[risu,1/3] ppc64.risu: Add missing byte and dword loads

Message ID 20180306064210.26157-1-sandipan@linux.vnet.ibm.com
State New
Headers show
Series [risu,1/3] ppc64.risu: Add missing byte and dword loads | expand

Commit Message

Sandipan Das March 6, 2018, 6:42 a.m. UTC 
The patterns for the following instructions are added:
 * Load Byte and Zero (lbz)
 * Load Byte and Zero with Update (lbzu)
 * Load Byte and Zero Indexed (lbzx)
 * Load Byte and Zero with Update Indexed (lbzux)
 * Load Doubleword (ld)

Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---
 ppc64.risu | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

Comments

Peter Maydell March 6, 2018, 11:39 a.m. UTC | #1 
On 6 March 2018 at 06:42, Sandipan Das <sandipan@linux.vnet.ibm.com> wrote:
> The patterns for the following instructions are added:
>  * Load Byte and Zero (lbz)
>  * Load Byte and Zero with Update (lbzu)
>  * Load Byte and Zero Indexed (lbzx)
>  * Load Byte and Zero with Update Indexed (lbzux)
>  * Load Doubleword (ld)
>
> Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>

Hi -- this patchset doesn't seem to have a cover letter. Could
you resend it with one, please? Our automated patch handling
tools all expect a cover letter if there's more than one patch
in a set.

thanks
-- PMM
Sandipan Das March 6, 2018, 11:42 a.m. UTC | #2 
On 03/06/2018 05:09 PM, Peter Maydell wrote:
> On 6 March 2018 at 06:42, Sandipan Das <sandipan@linux.vnet.ibm.com> wrote:
>> The patterns for the following instructions are added:
>>  * Load Byte and Zero (lbz)
>>  * Load Byte and Zero with Update (lbzu)
>>  * Load Byte and Zero Indexed (lbzx)
>>  * Load Byte and Zero with Update Indexed (lbzux)
>>  * Load Doubleword (ld)
>>
>> Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
> 
> Hi -- this patchset doesn't seem to have a cover letter. Could
> you resend it with one, please? Our automated patch handling
> tools all expect a cover letter if there's more than one patch
> in a set.
> 
> thanks
> -- PMM
> 
> 

Sure

--
With Regards,
Sandipan
diff mbox series

Patch

diff --git a/ppc64.risu b/ppc64.risu
index e2fd4f6..13b95ac 100644
--- a/ppc64.risu
+++ b/ppc64.risu
@@ -887,6 +887,31 @@  FTSQRT PPC64LE 111111 bf:3 0000000 frb:5 00101000000
 ISEL PPC64LE 011111 rt:5 ra:5 rb:5 bc:5 011110 \
 !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13; }
 
+# format:D book:I page:48 v:P1 lbz Load Byte & Zero
+LBZ PPC64LE 100010 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:D book:I page:48 v:P1 lbzu Load Byte & Zero with Update
+LBZU PPC64LE 100011 rt:5 ra:5 imm:16 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 32752; } \
+!memory { reg_plus_imm($ra, $imm); }
+
+# format:X book:I page:49 v:P1 lbzux Load Byte & Zero with Update Indexed
+LBZUX PPC64LE 011111 rt:5 ra:5 rb:5 00011101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:X book:I page:49 v:P1 lbzx Load Byte & Zero Indexed
+LBZX PPC64LE 011111 rt:5 ra:5 rb:5 00010101110 \
+!constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \
+!memory { reg_plus_reg($ra, $rb); }
+
+# format:DS book:I page:53 PPC ld Load Dword
+LD PPC64LE 111010 rt:5 ra:5 imm:14 00 \
+!constraints { $rt != 1 && $ra != 1 && $rt != 13 && $ra != 13 && $ra != 0 && $ra != $rt && $imm <= 8176; } \
+!memory { reg_plus_imm($ra, $imm << 2); }
+
 # format:X book:I page:62 v2.06 ldbrx Load Dword Byte-Reverse Indexed
 LDBRX PPC64LE 011111 rt:5 ra:5 rb:5 10000101000 \
 !constraints { $rt != 1 && $ra != 1 && $rb != 1 && $rt != 13 && $ra != 13 && $rb != 13 && $ra != 0 && $ra != $rt && $ra != $rb && $rt != $rb; } \