diff mbox series

[v7,02/20] target/mips: Define a bit for MXU in insn_flags

Message ID 1540383527-7923-3-git-send-email-aleksandar.markovic@rt-rk.com
State New
Headers show
Series target/mips: Add limited support for Ingenic's MXU ASE | expand

Commit Message

Aleksandar Markovic Oct. 24, 2018, 12:18 p.m. UTC 
From: Craig Janeczek <jancraig@amazon.com>

Define a bit for MXU in insn_flags. This is the first non-MIPS
(third party) ASE supported in QEMU for MIPS, so it is placed in
the section "bits 56-63: vendor-specific ASEs".

Signed-off-by: Craig Janeczek <jancraig@amazon.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
 target/mips/mips-defs.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Aleksandar Markovic Oct. 28, 2018, 6:05 p.m. UTC | #1 
> Subject: [PATCH v7 02/20] target/mips: Define a bit for MXU in insn_flags
> 
> From: Craig Janeczek <jancraig@amazon.com>
> 
> Define a bit for MXU in insn_flags. This is the first non-MIPS
> (third party) ASE supported in QEMU for MIPS, so it is placed in
> the section "bits 56-63: vendor-specific ASEs".
> 
> Signed-off-by: Craig Janeczek <jancraig@amazon.com>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---

Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
diff mbox series

Patch

diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h
index 5177618..dbdb4b2 100644
--- a/target/mips/mips-defs.h
+++ b/target/mips/mips-defs.h
@@ -69,6 +69,7 @@ 
  *   bits 56-63: vendor-specific ASEs
  */
 #define ASE_MMI           0x0100000000000000ULL
+#define ASE_MXU           0x0200000000000000ULL
 
 /* MIPS CPU defines. */
 #define		CPU_MIPS1	(ISA_MIPS1)