Show patches with: Series = target/mips: Add limited support for Ingenic's MXU ASE       |    State = Action Required       |    Archived = No       |   20 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v7,20/20] target/mips: Amend MXU ASE overview note target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,19/20] target/mips: Move MXU_EN check one level higher target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,18/20] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,17/20] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,16/20] target/mips: Add emulation of MXU instruction D16MAC target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,15/20] target/mips: Add emulation of MXU instruction D16MUL target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,14/20] target/mips: Add emulation of MXU instruction S8LDD target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,13/20] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,12/20] target/mips: Add emulation of MXU instructions S32I2M and S32M2I target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,11/20] target/mips: Add emulation of non-MXU MULL within MXU decoding engine target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,10/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn3' target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,09/20] target/mips: Add bit encoding for MXU operand getting pattern 'optn2' target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,08/20] target/mips: Add bit encoding for MXU execute add/sub pattern 'eptn2' target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,07/20] target/mips: Add bit encoding for MXU accumulate add/sub 2-bit pattern 'aptn2' target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,06/20] target/mips: Add bit encoding for MXU accumulate add/sub 1-bit pattern 'aptn1' target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,05/20] target/mips: Add MXU decoding engine target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,04/20] target/mips: Add and integrate MXU decoding engine placeholder target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,03/20] target/mips: Amend MXU instruction opcodes target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,02/20] target/mips: Define a bit for MXU in insn_flags target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New
[v7,01/20] target/mips: Introduce MXU registers target/mips: Add limited support for Ingenic's MXU ASE - - 1 - --- 2018-10-24 Aleksandar Markovic New