| Message ID | 1524699938-6764-15-git-send-email-mjc@sifive.com |
|---|---|
| State | New |
| Headers | show |
| Series | QEMU 2.13 Privileged ISA emulation updates | expand |
On Wed, Apr 25, 2018 at 4:53 PM Michael Clark <mjc@sifive.com> wrote: > Section 22.8 Subset Naming Convention of the RISC-V ISA Specification > defines the canonical order for extensions in the ISA string. It is > silent on the position of the E extension however E is a substitute > for I so it must come early in the extension list order. A comment > is added to state E and I are mutually exclusive, as the E extension > will be added to the RISC-V port in the future. > Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> > Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> > Cc: Palmer Dabbelt <palmer@sifive.com> > Cc: Alistair Francis <Alistair.Francis@wdc.com> > Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 +- > target/riscv/cpu.h | 1 + > 2 files changed, 2 insertions(+), 1 deletion(-) > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 5a527fb..4e5a56d 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -26,7 +26,7 @@ > /* RISC-V CPU definitions */ > -static const char riscv_exts[26] = "IMAFDQECLBJTPVNSUHKORWXYZG"; > +static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; > const char * const riscv_int_regnames[] = { > "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f3f131b..890cd96 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -71,6 +71,7 @@ > #define RV(x) ((target_ulong)1 << (x - 'A')) > #define RVI RV('I') > +#define RVE RV('E') /* E and I are mutually exclusive */ > #define RVM RV('M') > #define RVA RV('A') > #define RVF RV('F') > -- > 2.7.0
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5a527fb..4e5a56d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -26,7 +26,7 @@ /* RISC-V CPU definitions */ -static const char riscv_exts[26] = "IMAFDQECLBJTPVNSUHKORWXYZG"; +static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; const char * const riscv_int_regnames[] = { "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f3f131b..890cd96 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -71,6 +71,7 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) #define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') #define RVA RV('A') #define RVF RV('F')
Section 22.8 Subset Naming Convention of the RISC-V ISA Specification defines the canonical order for extensions in the ISA string. It is silent on the position of the E extension however E is a substitute for I so it must come early in the extension list order. A comment is added to state E and I are mutually exclusive, as the E extension will be added to the RISC-V port in the future. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Alistair Francis <Alistair.Francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)