[v8,25/35] RISC-V: Move non-ops from op_helper to cpu_helper

This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
---
 target/riscv/Makefile.objs              |  2 +-
 target/riscv/{helper.c => cpu_helper.c} | 34 ++++++++++++++++++++++++++++++++-
 target/riscv/op_helper.c                | 33 --------------------------------
 3 files changed, 34 insertions(+), 35 deletions(-)
 rename target/riscv/{helper.c => cpu_helper.c} (95%)

On Wed, Apr 25, 2018 at 5:13 PM Michael Clark <mjc@sifive.com> wrote:

> This patch makes op_helper.c contain only instruction
> operation helpers used by translate.c and moves any
> unrelated cpu helpers into cpu_helper.c. No logic is
> changed by this patch.

> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
> Cc: Palmer Dabbelt <palmer@sifive.com>
> Cc: Alistair Francis <Alistair.Francis@wdc.com>
> Signed-off-by: Michael Clark <mjc@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>   target/riscv/Makefile.objs              |  2 +-
>   target/riscv/{helper.c => cpu_helper.c} | 34
++++++++++++++++++++++++++++++++-
>   target/riscv/op_helper.c                | 33
--------------------------------
>   3 files changed, 34 insertions(+), 35 deletions(-)
>   rename target/riscv/{helper.c => cpu_helper.c} (95%)

> diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
> index abd0a7c..fcc5d34 100644
> --- a/target/riscv/Makefile.objs
> +++ b/target/riscv/Makefile.objs
> @@ -1 +1 @@
> -obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o gdbstub.o
pmp.o
> +obj-y += translate.o op_helper.o cpu_helper.o cpu.o fpu_helper.o
gdbstub.o pmp.o
> diff --git a/target/riscv/helper.c b/target/riscv/cpu_helper.c
> similarity index 95%
> rename from target/riscv/helper.c
> rename to target/riscv/cpu_helper.c
> index 47d116e..fb3f7ef 100644
> --- a/target/riscv/helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1,5 +1,5 @@
>   /*
> - * RISC-V emulation helpers for qemu.
> + * RISC-V CPU helpers for qemu.
>    *
>    * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
>    * Copyright (c) 2017-2018 SiFive, Inc.
> @@ -72,6 +72,38 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)

>   #if !defined(CONFIG_USER_ONLY)

> +/* iothread_mutex must be held */
> +uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t
value)
> +{
> +    CPURISCVState *env = &cpu->env;
> +    uint32_t old_mip, new_mip;
> +
> +    do {
> +        old_mip = atomic_read(&env->mip);
> +        new_mip = (old_mip & ~mask) | (value & mask);
> +    } while (atomic_cmpxchg(&env->mip, old_mip, new_mip) != old_mip);
> +
> +    if (new_mip && !old_mip) {
> +        cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> +    } else if (!new_mip && old_mip) {
> +        cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> +    }
> +
> +    return old_mip;
> +}
> +
> +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> +{
> +    if (newpriv > PRV_M) {
> +        g_assert_not_reached();
> +    }
> +    if (newpriv == PRV_H) {
> +        newpriv = PRV_U;
> +    }
> +    /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> +    env->priv = newpriv;
> +}
> +
>   /* get_physical_address - get the physical address for this virtual
address
>    *
>    * Do a page table walk to obtain the physical address corresponding to a
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 2a7f045..4b4d62b 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -640,38 +640,6 @@ target_ulong helper_csrrc(CPURISCVState *env,
target_ulong src,

>   #ifndef CONFIG_USER_ONLY

> -/* iothread_mutex must be held */
> -uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t
value)
> -{
> -    CPURISCVState *env = &cpu->env;
> -    uint32_t old_mip, new_mip;
> -
> -    do {
> -        old_mip = atomic_read(&env->mip);
> -        new_mip = (old_mip & ~mask) | (value & mask);
> -    } while (atomic_cmpxchg(&env->mip, old_mip, new_mip) != old_mip);
> -
> -    if (new_mip && !old_mip) {
> -        cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> -    } else if (!new_mip && old_mip) {
> -        cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
> -    }
> -
> -    return old_mip;
> -}
> -
> -void riscv_set_mode(CPURISCVState *env, target_ulong newpriv)
> -{
> -    if (newpriv > PRV_M) {
> -        g_assert_not_reached();
> -    }
> -    if (newpriv == PRV_H) {
> -        newpriv = PRV_U;
> -    }
> -    /* tlb_flush is unnecessary as mode is contained in mmu_idx */
> -    env->priv = newpriv;
> -}
> -
>   target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb)
>   {
>       if (!(env->priv >= PRV_S)) {
> @@ -722,7 +690,6 @@ target_ulong helper_mret(CPURISCVState *env,
target_ulong cpu_pc_deb)
>       return retpc;
>   }

> -
>   void helper_wfi(CPURISCVState *env)
>   {
>       CPUState *cs = CPU(riscv_env_get_cpu(env));
> --
> 2.7.0