| Message ID | 1463202423-19943-1-git-send-email-tsunghan.tw@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 14 May 2016 at 06:07, Tsung-Han Lin <tsunghan.tw@gmail.com> wrote: > Fix the access rights of SP_EL2 and SP_EL1, which should be able to be > accessed from EL2 and EL1 respectively. > > Signed-off-by: Tsung-Han Lin <tsunghan.tw@gmail.com> > --- > target-arm/helper.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target-arm/helper.c b/target-arm/helper.c > index a2ab701ca5c2..8d4b03b5141b 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3326,7 +3326,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { > .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, > { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, > - .access = PL2_RW, .type = ARM_CP_ALIAS, > + .access = PL1_RW, .type = ARM_CP_ALIAS, > .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, > { .name = "SPSel", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, > @@ -3526,7 +3526,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0 }, > { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, > .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, > - .access = PL3_RW, .type = ARM_CP_ALIAS, > + .access = PL2_RW, .type = ARM_CP_ALIAS, > .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, > { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, The ARM ARM defines that SP_EL1 is accessible only from EL2 or higher via the system-register instructions, and SP_EL2 only from EL3 or higher (see table C5-7 on page C5-288 of the v8 ARM ARM DDI0487A.h, or the register description pages for the two registers). Why do you think this is a correct change? thanks -- PMM
2016-05-14 19:08 GMT+09:00 Peter Maydell <peter.maydell@linaro.org>: > > > The ARM ARM defines that SP_EL1 is accessible only from > EL2 or higher via the system-register instructions, and > SP_EL2 only from EL3 or higher (see table C5-7 on page > C5-288 of the v8 ARM ARM DDI0487A.h, or the register description > pages for the two registers). Why do you think this is a correct > change? > > Thanks for the correction. Seems like I misunderstood the spec. > thanks > -- PMM >
diff --git a/target-arm/helper.c b/target-arm/helper.c index a2ab701ca5c2..8d4b03b5141b 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3326,7 +3326,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, sp_el[0]) }, { .name = "SP_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0, - .access = PL2_RW, .type = ARM_CP_ALIAS, + .access = PL1_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, sp_el[1]) }, { .name = "SPSel", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0, @@ -3526,7 +3526,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .resetvalue = 0 }, { .name = "SP_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0, - .access = PL3_RW, .type = ARM_CP_ALIAS, + .access = PL2_RW, .type = ARM_CP_ALIAS, .fieldoffset = offsetof(CPUARMState, sp_el[2]) }, { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
Fix the access rights of SP_EL2 and SP_EL1, which should be able to be accessed from EL2 and EL1 respectively. Signed-off-by: Tsung-Han Lin <tsunghan.tw@gmail.com> --- target-arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)