| Message ID | 1443911939-2825-2-git-send-email-edgar.iglesias@gmail.com |
|---|---|
| State | New |
| Headers | show |
Edgar E. Iglesias <edgar.iglesias@gmail.com> writes: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index cc1578c..895f2c2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -278,6 +278,7 @@ typedef struct CPUARMState { > }; > uint64_t far_el[4]; > }; > + uint64_t hpfar_el2; > union { /* Translation result. */ > struct { > uint64_t _unused_par_0; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 8367997..5a5e5f0 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, > + .type = ARM_CP_CONST, .resetvalue = 0 }, So what happens if access_el3_aa32ns_aa64any thinks it is OK to access the register from EL3 when there is no EL2? What ensures we get RES0? > REGINFO_SENTINEL > }; > > @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0, > .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, > #endif > + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > REGINFO_SENTINEL > }; Otherwise: Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
On 7 October 2015 at 12:51, Alex Bennée <alex.bennee@linaro.org> wrote: > > Edgar E. Iglesias <edgar.iglesias@gmail.com> writes: > >> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >> >> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >> --- >> target-arm/cpu.h | 1 + >> target-arm/helper.c | 12 ++++++++++++ >> 2 files changed, 13 insertions(+) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index cc1578c..895f2c2 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -278,6 +278,7 @@ typedef struct CPUARMState { >> }; >> uint64_t far_el[4]; >> }; >> + uint64_t hpfar_el2; >> union { /* Translation result. */ >> struct { >> uint64_t _unused_par_0; >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 8367997..5a5e5f0 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >> + .type = ARM_CP_CONST, .resetvalue = 0 }, > > So what happens if access_el3_aa32ns_aa64any thinks it is OK to access > the register from EL3 when there is no EL2? What ensures we get RES0? ...the fact we've defined it as an RW CONST register with a resetvalue of zero? Or am I misunderstanding your question? thanks -- PMM
Hello, On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index cc1578c..895f2c2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -278,6 +278,7 @@ typedef struct CPUARMState { > }; > uint64_t far_el[4]; > }; > + uint64_t hpfar_el2; > union { /* Translation result. */ > struct { > uint64_t _unused_par_0; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 8367997..5a5e5f0 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > REGINFO_SENTINEL > }; > > @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0, > .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, > #endif > + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > REGINFO_SENTINEL > }; Shouldn't these last two registers be placed before the "#endif" which closes an "#ifndef CONFIG_USER_ONLY"? Thanks, Laurent
Peter Maydell <peter.maydell@linaro.org> writes: > On 7 October 2015 at 12:51, Alex Bennée <alex.bennee@linaro.org> wrote: >> >> Edgar E. Iglesias <edgar.iglesias@gmail.com> writes: >> >>> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >>> >>> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >>> --- >>> target-arm/cpu.h | 1 + >>> target-arm/helper.c | 12 ++++++++++++ >>> 2 files changed, 13 insertions(+) >>> >>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >>> index cc1578c..895f2c2 100644 >>> --- a/target-arm/cpu.h >>> +++ b/target-arm/cpu.h >>> @@ -278,6 +278,7 @@ typedef struct CPUARMState { >>> }; >>> uint64_t far_el[4]; >>> }; >>> + uint64_t hpfar_el2; >>> union { /* Translation result. */ >>> struct { >>> uint64_t _unused_par_0; >>> diff --git a/target-arm/helper.c b/target-arm/helper.c >>> index 8367997..5a5e5f0 100644 >>> --- a/target-arm/helper.c >>> +++ b/target-arm/helper.c >>> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >>> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >>> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >>> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >>> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >>> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >>> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >>> + .type = ARM_CP_CONST, .resetvalue = 0 }, >> >> So what happens if access_el3_aa32ns_aa64any thinks it is OK to access >> the register from EL3 when there is no EL2? What ensures we get RES0? > > ...the fact we've defined it as an RW CONST register with a resetvalue > of zero? Or am I misunderstanding your question? Nope you didn't misunderstand, I was being dim comparing with the later definitions ;-) Thanks. > > thanks > -- PMM
On 8 October 2015 at 06:38, Laurent Desnogues <laurent.desnogues@gmail.com> wrote: > Hello, > > On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias > <edgar.iglesias@gmail.com> wrote: >> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >> >> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >> --- >> target-arm/cpu.h | 1 + >> target-arm/helper.c | 12 ++++++++++++ >> 2 files changed, 13 insertions(+) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index cc1578c..895f2c2 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -278,6 +278,7 @@ typedef struct CPUARMState { >> }; >> uint64_t far_el[4]; >> }; >> + uint64_t hpfar_el2; >> union { /* Translation result. */ >> struct { >> uint64_t _unused_par_0; >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 8367997..5a5e5f0 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >> + .type = ARM_CP_CONST, .resetvalue = 0 }, >> REGINFO_SENTINEL >> }; >> >> @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { >> .resetvalue = 0, >> .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, >> #endif >> + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, >> + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, .accessfn = access_el3_aa32ns, >> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, >> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, >> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, >> REGINFO_SENTINEL >> }; > > Shouldn't these last two registers be placed before the "#endif" which > closes an "#ifndef CONFIG_USER_ONLY"? Mostly I've taken the approach that we only ifdef out regdefs which actually won't compile (the timer ones refer to functions which call softmmu-only timer related functions, for instance). Having regdefs for higher ELs in the USER_ONLY build is harmless; they just sit in the hash table and are never accessed. thanks -- PMM
Laurent Desnogues <laurent.desnogues@gmail.com> writes: > Hello, > > On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias > <edgar.iglesias@gmail.com> wrote: >> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >> >> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >> --- >> target-arm/cpu.h | 1 + >> target-arm/helper.c | 12 ++++++++++++ >> 2 files changed, 13 insertions(+) >> >> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >> index cc1578c..895f2c2 100644 >> --- a/target-arm/cpu.h >> +++ b/target-arm/cpu.h >> @@ -278,6 +278,7 @@ typedef struct CPUARMState { >> }; >> uint64_t far_el[4]; >> }; >> + uint64_t hpfar_el2; >> union { /* Translation result. */ >> struct { >> uint64_t _unused_par_0; >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 8367997..5a5e5f0 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >> + .type = ARM_CP_CONST, .resetvalue = 0 }, >> REGINFO_SENTINEL >> }; >> >> @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { >> .resetvalue = 0, >> .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, >> #endif >> + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, >> + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, .accessfn = access_el3_aa32ns, >> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, >> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, >> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >> + .access = PL2_RW, >> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, >> REGINFO_SENTINEL >> }; > > Shouldn't these last two registers be placed before the "#endif" which > closes an "#ifndef CONFIG_USER_ONLY"? There seem to be a bunch of _EL2 registers above the #ifndef as well so I'm not sure it matters. In fact won't the guest just trap if it tries? > > Thanks, > > Laurent
Edgar E. Iglesias <edgar.iglesias@gmail.com> writes: > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Now Peter has pointed out I can't read ;-) Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target-arm/cpu.h | 1 + > target-arm/helper.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index cc1578c..895f2c2 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -278,6 +278,7 @@ typedef struct CPUARMState { > }; > uint64_t far_el[4]; > }; > + uint64_t hpfar_el2; > union { /* Translation result. */ > struct { > uint64_t _unused_par_0; > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 8367997..5a5e5f0 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > REGINFO_SENTINEL > }; > > @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .resetvalue = 0, > .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, > #endif > + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, .accessfn = access_el3_aa32ns, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > + .access = PL2_RW, > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > REGINFO_SENTINEL > };
On Thu, Oct 8, 2015 at 10:24 AM, Alex Bennée <alex.bennee@linaro.org> wrote: > > Laurent Desnogues <laurent.desnogues@gmail.com> writes: > >> Hello, >> >> On Sun, Oct 4, 2015 at 12:38 AM, Edgar E. Iglesias >> <edgar.iglesias@gmail.com> wrote: >>> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> >>> >>> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> >>> --- >>> target-arm/cpu.h | 1 + >>> target-arm/helper.c | 12 ++++++++++++ >>> 2 files changed, 13 insertions(+) >>> >>> diff --git a/target-arm/cpu.h b/target-arm/cpu.h >>> index cc1578c..895f2c2 100644 >>> --- a/target-arm/cpu.h >>> +++ b/target-arm/cpu.h >>> @@ -278,6 +278,7 @@ typedef struct CPUARMState { >>> }; >>> uint64_t far_el[4]; >>> }; >>> + uint64_t hpfar_el2; >>> union { /* Translation result. */ >>> struct { >>> uint64_t _unused_par_0; >>> diff --git a/target-arm/helper.c b/target-arm/helper.c >>> index 8367997..5a5e5f0 100644 >>> --- a/target-arm/helper.c >>> +++ b/target-arm/helper.c >>> @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { >>> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, >>> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, >>> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, >>> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, >>> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >>> + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, >>> + .type = ARM_CP_CONST, .resetvalue = 0 }, >>> REGINFO_SENTINEL >>> }; >>> >>> @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { >>> .resetvalue = 0, >>> .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, >>> #endif >>> + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, >>> + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >>> + .access = PL2_RW, .accessfn = access_el3_aa32ns, >>> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, >>> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, >>> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, >>> + .access = PL2_RW, >>> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, >>> REGINFO_SENTINEL >>> }; >> >> Shouldn't these last two registers be placed before the "#endif" which >> closes an "#ifndef CONFIG_USER_ONLY"? > > There seem to be a bunch of _EL2 registers above the #ifndef as well so > I'm not sure it matters. In fact won't the guest just trap if it tries? That's correct. But over the years a lot of code has been added that is completely irrelevant to user mode. An interesting experiment is to check how the interrupt_request field of CPU is in fact not needed by arm-linux-user. You can prove it's only needed through a chain of calls that originate from omap_wfi_write which is PL1_RW. I agree it's not a big deal, it's most likely only me who finds it ugly and inefficient that an interrupt request field exists in user mode :-) Anyway this in no case is a reason to not ack Edgar patch. Laurent
On Thu, Oct 08, 2015 at 10:14:08AM +0100, Alex Bennée wrote: > > Edgar E. Iglesias <edgar.iglesias@gmail.com> writes: > > > From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com> > > > > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > Now Peter has pointed out I can't read ;-) > > Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Thanks for all the clarifications, I'll add your RB to my series. Best regards, Edgar > > > --- > > target-arm/cpu.h | 1 + > > target-arm/helper.c | 12 ++++++++++++ > > 2 files changed, 13 insertions(+) > > > > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > > index cc1578c..895f2c2 100644 > > --- a/target-arm/cpu.h > > +++ b/target-arm/cpu.h > > @@ -278,6 +278,7 @@ typedef struct CPUARMState { > > }; > > uint64_t far_el[4]; > > }; > > + uint64_t hpfar_el2; > > union { /* Translation result. */ > > struct { > > uint64_t _unused_par_0; > > diff --git a/target-arm/helper.c b/target-arm/helper.c > > index 8367997..5a5e5f0 100644 > > --- a/target-arm/helper.c > > +++ b/target-arm/helper.c > > @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > > { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, > > .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, > > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, > > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > > + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, > > + .type = ARM_CP_CONST, .resetvalue = 0 }, > > REGINFO_SENTINEL > > }; > > > > @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > > .resetvalue = 0, > > .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, > > #endif > > + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, > > + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > > + .access = PL2_RW, .accessfn = access_el3_aa32ns, > > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > > + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, > > + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, > > + .access = PL2_RW, > > + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, > > REGINFO_SENTINEL > > }; > > -- > Alex Bennée
diff --git a/target-arm/cpu.h b/target-arm/cpu.h index cc1578c..895f2c2 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -278,6 +278,7 @@ typedef struct CPUARMState { }; uint64_t far_el[4]; }; + uint64_t hpfar_el2; union { /* Translation result. */ struct { uint64_t _unused_par_0; diff --git a/target-arm/helper.c b/target-arm/helper.c index 8367997..5a5e5f0 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -3223,6 +3223,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1, .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, + .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any, + .type = ARM_CP_CONST, .resetvalue = 0 }, REGINFO_SENTINEL }; @@ -3444,6 +3448,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .resetvalue = 0, .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write }, #endif + { .name = "HPFAR", .state = ARM_CP_STATE_AA32, + .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, + .access = PL2_RW, .accessfn = access_el3_aa32ns, + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64, + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) }, REGINFO_SENTINEL };