| Message ID | 1440516223-16864-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 25 August 2015 at 16:23, Peter Maydell <peter.maydell@linaro.org> wrote: > Here's the ARM queue. I know I have a pile of backed-up code > review to do, but I wanted to get these patches out rather > than accumulating a fifty-patch queue... > > This is v2: only change is to drop the two smbios patches. v2 applied to master. -- PMM
Here's the ARM queue. I know I have a pile of backed-up code review to do, but I wanted to get these patches out rather than accumulating a fifty-patch queue... This is v2: only change is to drop the two smbios patches. thanks -- PMM The following changes since commit 34a4450434f1a5daee06fca223afcbb9c8f1ee24: Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20150824' into staging (2015-08-25 13:34:57 +0100) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20150825-1 for you to fetch changes up to cea66e91212164e02ad1d245c2371f7e8eb59e7f: target-arm: Implement AArch64 TLBI operations on IPAs (2015-08-25 16:18:33 +0100) ---------------------------------------------------------------- target-arm queue: * add missing EL2/EL3 TLBI operations * add missing EL2/EL3 ATS operations * add missing EL2/EL3 registers * update Xilinx MAINTAINERS info * Xilinx: connect the four OCM banks ---------------------------------------------------------------- Alistair Francis (3): xlnx-zynqmp: Connect the four OCM banks MAINTAINERS: Update Xilinx Maintainership MAINTAINERS: Add ZynqMP to MAINTAINERS file Peter Maydell (15): target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers target-arm: Implement missing AMAIR registers target-arm: Implement missing AFSR registers target-arm: Implement missing ACTLR registers target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations target-arm: Wire up AArch64 EL2 and EL3 address translation ops target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 target-arm: Enable the AArch32 ATS12NSO ops target-arm: Implement AArch32 ATS1H* operations cputlb: Add functions for flushing TLB for a single MMU index target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Implement missing EL2 TLBI operations target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement AArch64 TLBI operations on IPAs MAINTAINERS | 27 ++- cputlb.c | 97 +++++++++ hw/arm/xlnx-zynqmp.c | 15 ++ include/exec/exec-all.h | 47 +++++ include/hw/arm/xlnx-zynqmp.h | 6 + target-arm/cpu.h | 3 + target-arm/helper.c | 489 ++++++++++++++++++++++++++++++++++++++----- target-arm/op_helper.c | 8 + 8 files changed, 629 insertions(+), 63 deletions(-)