| Message ID | 1440433079-14458-28-git-send-email-rth@twiddle.net |
|---|---|
| State | New |
| Headers | show |
On 24 August 2015 at 17:17, Richard Henderson <rth@twiddle.net> wrote: > Signed-off-by: Richard Henderson <rth@twiddle.net> > --- > target-tilegx/translate.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c > index 51ee158..af4b34a 100644 > --- a/target-tilegx/translate.c > +++ b/target-tilegx/translate.c > @@ -647,11 +647,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, > case OE_RRR(FSINGLE_MUL2, 0, X0): > case OE_RRR(FSINGLE_PACK2, 0, X0): > case OE_RRR(FSINGLE_SUB1, 0, X0): > + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; > case OE_RRR(MNZ, 0, X0): > case OE_RRR(MNZ, 0, X1): > case OE_RRR(MNZ, 4, Y0): > case OE_RRR(MNZ, 4, Y1): > - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; > + t0 = load_zero(dc); > + tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0); > + mnemonic = "mnz"; > + break; > case OE_RRR(MULAX, 0, X0): > case OE_RRR(MULAX, 3, Y0): > tcg_gen_mul_tl(tdest, tsrca, tsrcb); > @@ -767,7 +771,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, > case OE_RRR(MZ, 0, X1): > case OE_RRR(MZ, 4, Y0): > case OE_RRR(MZ, 4, Y1): > - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; > + t0 = load_zero(dc); > + tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0); > + mnemonic = "mz"; > + break; > case OE_RRR(NOR, 0, X0): > case OE_RRR(NOR, 0, X1): > case OE_RRR(NOR, 5, Y0): > -- > 2.4.3 > I *think* this code is correct, but the ISA manual perplexes me entirely. Why on earth would you describe anything as "compute the boolean AND of something with a value of all ones", when that's just a no-op? I can't see what I'm missing that means they didn't just describe 'mz' as "dest = srcA ? srcB : 0". Reviewed-by: Peter Maydell <peter.maydell@linaro.org> thanks -- PMM
On 08/30/2015 06:52 AM, Peter Maydell wrote: > I *think* this code is correct, but the ISA manual perplexes me > entirely. Why on earth would you describe anything as "compute > the boolean AND of something with a value of all ones", when that's > just a no-op? I can't see what I'm missing that means they > didn't just describe 'mz' as "dest = srcA ? srcB : 0". Clearly someone who decided that was the best way to implement a conditional move in hardware. The language just propagated back to the manual. r~
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c index 51ee158..af4b34a 100644 --- a/target-tilegx/translate.c +++ b/target-tilegx/translate.c @@ -647,11 +647,15 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(FSINGLE_MUL2, 0, X0): case OE_RRR(FSINGLE_PACK2, 0, X0): case OE_RRR(FSINGLE_SUB1, 0, X0): + return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; case OE_RRR(MNZ, 0, X0): case OE_RRR(MNZ, 0, X1): case OE_RRR(MNZ, 4, Y0): case OE_RRR(MNZ, 4, Y1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + t0 = load_zero(dc); + tcg_gen_movcond_tl(TCG_COND_NE, tdest, tsrca, t0, tsrcb, t0); + mnemonic = "mnz"; + break; case OE_RRR(MULAX, 0, X0): case OE_RRR(MULAX, 3, Y0): tcg_gen_mul_tl(tdest, tsrca, tsrcb); @@ -767,7 +771,10 @@ static TileExcp gen_rrr_opcode(DisasContext *dc, unsigned opext, case OE_RRR(MZ, 0, X1): case OE_RRR(MZ, 4, Y0): case OE_RRR(MZ, 4, Y1): - return TILEGX_EXCP_OPCODE_UNIMPLEMENTED; + t0 = load_zero(dc); + tcg_gen_movcond_tl(TCG_COND_EQ, tdest, tsrca, t0, tsrcb, t0); + mnemonic = "mz"; + break; case OE_RRR(NOR, 0, X0): case OE_RRR(NOR, 0, X1): case OE_RRR(NOR, 5, Y0):
Signed-off-by: Richard Henderson <rth@twiddle.net> --- target-tilegx/translate.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)