| Message ID | 1340195241-16620-1-git-send-email-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
On Wed, Jun 20, 2012 at 12:26 PM, Peter Maydell <peter.maydell@linaro.org> wrote: > This is a pullreq for outstanding target-arm patches. In fact it > only has my cp15 rework series in it. (No changes in that since the > v2 series I sent out some weeks back except for a tiny trivial fix > for a textual rebase conflict.) > > Please pull. Thanks, pulled. > > -- PMM > > > The following changes since commit 93bfef4c6e4b23caea9d51e1099d06433d8835a4: > > Allow machines to configure the QEMU_VERSION that's exposed via hardware (2012-06-19 13:36:56 -0500) > > are available in the git repository at: > git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream > > Peter Maydell (33): > target-arm: Fix 11MPCore cache type register value > target-arm: initial coprocessor register framework > hw/pxa2xx: Convert cp14 perf registers to new scheme > hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs > hw/pxa2xx_pic: Convert coprocessor registers to new scheme > target-arm: Remove old cpu_arm_set_cp_io infrastructure > target-arm: Add register_cp_regs_for_features() > target-arm: Convert debug registers to cp_reginfo > target-arm: Convert TEECR, TEEHBR to new scheme > target-arm: Convert WFI/barriers special cases to cp_reginfo > target-arm: Convert TLS registers > target-arm: Convert performance monitor registers > target-arm: Convert generic timer cp15 regs > target-arm: Convert cp15 c3 register > target-arm: Convert MMU fault status cp15 registers > target-arm: Convert cp15 crn=2 registers > target-arm: Convert cp15 crn=13 registers > target-arm: Convert cp15 crn=10 registers > target-arm: Convert cp15 crn=15 registers > target-arm: Convert cp15 MMU TLB control > target-arm: Convert cp15 VA-PA translation registers > target-arm: convert cp15 crn=7 registers > target-arm: Convert cp15 crn=6 registers > target-arm: Convert cp15 crn=9 registers > target-arm: Convert cp15 crn=1 registers > target-arm: Convert cp15 crn=0 crm={1,2} feature registers > target-arm: Convert cp15 cache ID registers > target-arm: Convert MPIDR > target-arm: Convert final ID registers > target-arm: Remove c0_cachetype CPUARMState field > target-arm: Move block cache ops to new cp15 framework > target-arm: Remove remaining old cp15 infrastructure > target-arm: Remove ARM_CPUID_* macros > > hw/pxa2xx.c | 285 +++---- > hw/pxa2xx_pic.c | 53 +- > linux-user/cpu-uname.c | 5 +- > target-arm/cpu-qom.h | 5 + > target-arm/cpu.c | 230 +++++-- > target-arm/cpu.h | 248 +++++- > target-arm/helper.c | 2070 +++++++++++++++++++++++++++--------------------- > target-arm/helper.h | 11 +- > target-arm/machine.c | 2 - > target-arm/op_helper.c | 42 +- > target-arm/translate.c | 474 ++++-------- > 11 files changed, 1889 insertions(+), 1536 deletions(-)
This is a pullreq for outstanding target-arm patches. In fact it only has my cp15 rework series in it. (No changes in that since the v2 series I sent out some weeks back except for a tiny trivial fix for a textual rebase conflict.) Please pull. -- PMM The following changes since commit 93bfef4c6e4b23caea9d51e1099d06433d8835a4: Allow machines to configure the QEMU_VERSION that's exposed via hardware (2012-06-19 13:36:56 -0500) are available in the git repository at: git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream Peter Maydell (33): target-arm: Fix 11MPCore cache type register value target-arm: initial coprocessor register framework hw/pxa2xx: Convert cp14 perf registers to new scheme hw/pxa2xx.c: Convert CLKCFG and PWRMODE cp14 regs hw/pxa2xx_pic: Convert coprocessor registers to new scheme target-arm: Remove old cpu_arm_set_cp_io infrastructure target-arm: Add register_cp_regs_for_features() target-arm: Convert debug registers to cp_reginfo target-arm: Convert TEECR, TEEHBR to new scheme target-arm: Convert WFI/barriers special cases to cp_reginfo target-arm: Convert TLS registers target-arm: Convert performance monitor registers target-arm: Convert generic timer cp15 regs target-arm: Convert cp15 c3 register target-arm: Convert MMU fault status cp15 registers target-arm: Convert cp15 crn=2 registers target-arm: Convert cp15 crn=13 registers target-arm: Convert cp15 crn=10 registers target-arm: Convert cp15 crn=15 registers target-arm: Convert cp15 MMU TLB control target-arm: Convert cp15 VA-PA translation registers target-arm: convert cp15 crn=7 registers target-arm: Convert cp15 crn=6 registers target-arm: Convert cp15 crn=9 registers target-arm: Convert cp15 crn=1 registers target-arm: Convert cp15 crn=0 crm={1,2} feature registers target-arm: Convert cp15 cache ID registers target-arm: Convert MPIDR target-arm: Convert final ID registers target-arm: Remove c0_cachetype CPUARMState field target-arm: Move block cache ops to new cp15 framework target-arm: Remove remaining old cp15 infrastructure target-arm: Remove ARM_CPUID_* macros hw/pxa2xx.c | 285 +++---- hw/pxa2xx_pic.c | 53 +- linux-user/cpu-uname.c | 5 +- target-arm/cpu-qom.h | 5 + target-arm/cpu.c | 230 +++++-- target-arm/cpu.h | 248 +++++- target-arm/helper.c | 2070 +++++++++++++++++++++++++++--------------------- target-arm/helper.h | 11 +- target-arm/machine.c | 2 - target-arm/op_helper.c | 42 +- target-arm/translate.c | 474 ++++-------- 11 files changed, 1889 insertions(+), 1536 deletions(-)