diff mbox series

[1/1] target/riscv: Fix VS mode interrupts forwarding.

Message ID 0c4859f90948ba392da456c9e1daf8fde8f5b22e.1582453384.git.rajnesh.kanwal49@gmail.com
State New
Headers show
Series [1/1] target/riscv: Fix VS mode interrupts forwarding. | expand

Commit Message

Rajnesh Kanwal Feb. 23, 2020, 10:28 a.m. UTC 
From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>

Currently riscv_cpu_local_irq_pending is used to find out pending
interrupt and VS mode interrupts are being shifted to represent
S mode interrupts in this function. So when the cause returned by
this function is passed to riscv_cpu_do_interrupt to actually
forward the interrupt, the VS mode forwarding check does not work
as intended and interrupt is actually forwarded to hypervisor. This
patch fixes this issue.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
---
 target/riscv/cpu_helper.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

Jose Martins Feb. 23, 2020, 2:40 p.m. UTC | #1 
Hello rajnesh,

I had already submitted almost this exact patch a few weeks ago.

Jose

On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
>
> From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>
> Currently riscv_cpu_local_irq_pending is used to find out pending
> interrupt and VS mode interrupts are being shifted to represent
> S mode interrupts in this function. So when the cause returned by
> this function is passed to riscv_cpu_do_interrupt to actually
> forward the interrupt, the VS mode forwarding check does not work
> as intended and interrupt is actually forwarded to hypervisor. This
> patch fixes this issue.
>
> Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> ---
>  target/riscv/cpu_helper.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index b9e90dfd9a..59535ecba6 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
>      target_ulong pending = env->mip & env->mie &
>                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
>      target_ulong vspending = (env->mip & env->mie &
> -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
> +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
>
>      target_ulong mie    = env->priv < PRV_M ||
>                            (env->priv == PRV_M && mstatus_mie);
> @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>
>              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
>                  !force_hs_execp) {
> +                /*
> +                 * See if we need to adjust cause. Yes if its VS mode interrupt
> +                 * no if hypervisor has delegated one of hs mode's interrupt
> +                 */
> +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> +                    cause == IRQ_VS_EXT)
> +                    cause = cause - 1;
>                  /* Trap to VS mode */
>              } else if (riscv_cpu_virt_enabled(env)) {
>                  /* Trap into HS mode, from virt */
> --
> 2.17.1
>
>
Rajnesh Kanwal Feb. 23, 2020, 3:10 p.m. UTC | #2 
Hello Jose,

Sorry I didn't see that as it hadn't became a part of the port. I don't
know how
they proceed with same patches.

Just to add, there is a minor problem with your patch. The cause value
should
only be decremented by one for VS mode interrupts. In case if hypervisor has
delegated S mode interrupts then we should not decrement cause for those
interrupts.

Regards,
Rajnesh


On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com>
wrote:

> Hello rajnesh,
>
> I had already submitted almost this exact patch a few weeks ago.
>
> Jose
>
> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
> >
> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> >
> > Currently riscv_cpu_local_irq_pending is used to find out pending
> > interrupt and VS mode interrupts are being shifted to represent
> > S mode interrupts in this function. So when the cause returned by
> > this function is passed to riscv_cpu_do_interrupt to actually
> > forward the interrupt, the VS mode forwarding check does not work
> > as intended and interrupt is actually forwarded to hypervisor. This
> > patch fixes this issue.
> >
> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> > ---
> >  target/riscv/cpu_helper.c | 9 ++++++++-
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index b9e90dfd9a..59535ecba6 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState
> *env)
> >      target_ulong pending = env->mip & env->mie &
> >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
> >      target_ulong vspending = (env->mip & env->mie &
> > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
> > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
> >
> >      target_ulong mie    = env->priv < PRV_M ||
> >                            (env->priv == PRV_M && mstatus_mie);
> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >
> >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1)
> &&
> >                  !force_hs_execp) {
> > +                /*
> > +                 * See if we need to adjust cause. Yes if its VS mode
> interrupt
> > +                 * no if hypervisor has delegated one of hs mode's
> interrupt
> > +                 */
> > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> > +                    cause == IRQ_VS_EXT)
> > +                    cause = cause - 1;
> >                  /* Trap to VS mode */
> >              } else if (riscv_cpu_virt_enabled(env)) {
> >                  /* Trap into HS mode, from virt */
> > --
> > 2.17.1
> >
> >
>
Jose Martins Feb. 23, 2020, 3:39 p.m. UTC | #3 
No problem. But I'm failing to see what you mean. My reasoning was:
the specification mandates that only VS mode interrupt bits are
writable in hideleg, all the others must be hardwired to zero. This
means the hypervisor can't really delegate S mode interrupts as you
are saying. So, if this is implemented correctly, you will never get
inside that if condition because of an HS interrupt. And all
delegatable asynchronous exception values must be decremented. So,
checking if this is an async exception should do the job.

Jose

On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <rajnesh.kanwal49@gmail.com> wrote:
>
> Hello Jose,
>
> Sorry I didn't see that as it hadn't became a part of the port. I don't know how
> they proceed with same patches.
>
> Just to add, there is a minor problem with your patch. The cause value should
> only be decremented by one for VS mode interrupts. In case if hypervisor has
> delegated S mode interrupts then we should not decrement cause for those
> interrupts.
>
> Regards,
> Rajnesh
>
>
> On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com> wrote:
>>
>> Hello rajnesh,
>>
>> I had already submitted almost this exact patch a few weeks ago.
>>
>> Jose
>>
>> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
>> >
>> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>> >
>> > Currently riscv_cpu_local_irq_pending is used to find out pending
>> > interrupt and VS mode interrupts are being shifted to represent
>> > S mode interrupts in this function. So when the cause returned by
>> > this function is passed to riscv_cpu_do_interrupt to actually
>> > forward the interrupt, the VS mode forwarding check does not work
>> > as intended and interrupt is actually forwarded to hypervisor. This
>> > patch fixes this issue.
>> >
>> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>> > ---
>> >  target/riscv/cpu_helper.c | 9 ++++++++-
>> >  1 file changed, 8 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> > index b9e90dfd9a..59535ecba6 100644
>> > --- a/target/riscv/cpu_helper.c
>> > +++ b/target/riscv/cpu_helper.c
>> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
>> >      target_ulong pending = env->mip & env->mie &
>> >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
>> >      target_ulong vspending = (env->mip & env->mie &
>> > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
>> > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
>> >
>> >      target_ulong mie    = env->priv < PRV_M ||
>> >                            (env->priv == PRV_M && mstatus_mie);
>> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> >
>> >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
>> >                  !force_hs_execp) {
>> > +                /*
>> > +                 * See if we need to adjust cause. Yes if its VS mode interrupt
>> > +                 * no if hypervisor has delegated one of hs mode's interrupt
>> > +                 */
>> > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
>> > +                    cause == IRQ_VS_EXT)
>> > +                    cause = cause - 1;
>> >                  /* Trap to VS mode */
>> >              } else if (riscv_cpu_virt_enabled(env)) {
>> >                  /* Trap into HS mode, from virt */
>> > --
>> > 2.17.1
>> >
>> >
Rajnesh Kanwal Feb. 24, 2020, 10:13 a.m. UTC | #4 
Nice catch. You are right. I was a bit confused after looking at current
xvisor and KVM port. They are delegating S mode interrupts to VS mode, as
per my understanding after looking at
https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c
line no. 34. I will see if there is a way to decline a patch.

Thanks for pointing that out.
Regards,
Rajnesh

On Sun, Feb 23, 2020 at 8:40 PM Jose Martins <josemartins90@gmail.com>
wrote:

> No problem. But I'm failing to see what you mean. My reasoning was:
> the specification mandates that only VS mode interrupt bits are
> writable in hideleg, all the others must be hardwired to zero. This
> means the hypervisor can't really delegate S mode interrupts as you
> are saying. So, if this is implemented correctly, you will never get
> inside that if condition because of an HS interrupt. And all
> delegatable asynchronous exception values must be decremented. So,
> checking if this is an async exception should do the job.
>
> Jose
>
> On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> wrote:
> >
> > Hello Jose,
> >
> > Sorry I didn't see that as it hadn't became a part of the port. I don't
> know how
> > they proceed with same patches.
> >
> > Just to add, there is a minor problem with your patch. The cause value
> should
> > only be decremented by one for VS mode interrupts. In case if hypervisor
> has
> > delegated S mode interrupts then we should not decrement cause for those
> > interrupts.
> >
> > Regards,
> > Rajnesh
> >
> >
> > On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <josemartins90@gmail.com>
> wrote:
> >>
> >> Hello rajnesh,
> >>
> >> I had already submitted almost this exact patch a few weeks ago.
> >>
> >> Jose
> >>
> >> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
> >> >
> >> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> >> >
> >> > Currently riscv_cpu_local_irq_pending is used to find out pending
> >> > interrupt and VS mode interrupts are being shifted to represent
> >> > S mode interrupts in this function. So when the cause returned by
> >> > this function is passed to riscv_cpu_do_interrupt to actually
> >> > forward the interrupt, the VS mode forwarding check does not work
> >> > as intended and interrupt is actually forwarded to hypervisor. This
> >> > patch fixes this issue.
> >> >
> >> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> >> > ---
> >> >  target/riscv/cpu_helper.c | 9 ++++++++-
> >> >  1 file changed, 8 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> >> > index b9e90dfd9a..59535ecba6 100644
> >> > --- a/target/riscv/cpu_helper.c
> >> > +++ b/target/riscv/cpu_helper.c
> >> > @@ -46,7 +46,7 @@ static int
> riscv_cpu_local_irq_pending(CPURISCVState *env)
> >> >      target_ulong pending = env->mip & env->mie &
> >> >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
> >> >      target_ulong vspending = (env->mip & env->mie &
> >> > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP))
> >> 1;
> >> > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
> >> >
> >> >      target_ulong mie    = env->priv < PRV_M ||
> >> >                            (env->priv == PRV_M && mstatus_mie);
> >> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >> >
> >> >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) &
> 1) &&
> >> >                  !force_hs_execp) {
> >> > +                /*
> >> > +                 * See if we need to adjust cause. Yes if its VS
> mode interrupt
> >> > +                 * no if hypervisor has delegated one of hs mode's
> interrupt
> >> > +                 */
> >> > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> >> > +                    cause == IRQ_VS_EXT)
> >> > +                    cause = cause - 1;
> >> >                  /* Trap to VS mode */
> >> >              } else if (riscv_cpu_virt_enabled(env)) {
> >> >                  /* Trap into HS mode, from virt */
> >> > --
> >> > 2.17.1
> >> >
> >> >
>
Anup Patel Feb. 24, 2020, 11:05 a.m. UTC | #5 
Hi,

Yes, indeed this has to be fixed in QEMU, Xvisor and KVM.

Before fixing Xvisor and KVM, we have to first fix this in QEMU.

For Xvisor RISC-V, feel free to send patch to Xvisor-devel@googlegroups.com
For KVM RISC-V, I will update it in v11 patch series and KVM RISC-V git repo as well.

Regards,
Anup

From: Qemu-riscv <qemu-riscv-bounces+anup.patel=wdc.com@nongnu.org> On Behalf Of Rajnesh Kanwal
Sent: Monday, February 24, 2020 3:44 PM
To: Jose Martins <josemartins90@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>; palmerdabbelt@google.com; qemu-riscv@nongnu.org; qemu-devel@nongnu.org
Subject: Re: [PATCH 1/1] target/riscv: Fix VS mode interrupts forwarding.

Nice catch. You are right. I was a bit confused after looking at current xvisor and KVM port. They are delegating S mode interrupts to VS mode, as per my understanding after looking at https://github.com/kvm-riscv/linux/blob/riscv_kvm_master/arch/riscv/kvm/main.c line no. 34. I will see if there is a way to decline a patch. 
Thanks for pointing that out.
Regards,
Rajnesh

On Sun, Feb 23, 2020 at 8:40 PM Jose Martins <mailto:josemartins90@gmail.com> wrote:
No problem. But I'm failing to see what you mean. My reasoning was:
the specification mandates that only VS mode interrupt bits are
writable in hideleg, all the others must be hardwired to zero. This
means the hypervisor can't really delegate S mode interrupts as you
are saying. So, if this is implemented correctly, you will never get
inside that if condition because of an HS interrupt. And all
delegatable asynchronous exception values must be decremented. So,
checking if this is an async exception should do the job.

Jose

On Sun, 23 Feb 2020 at 15:10, Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com> wrote:
>
> Hello Jose,
>
> Sorry I didn't see that as it hadn't became a part of the port. I don't know how
> they proceed with same patches.
>
> Just to add, there is a minor problem with your patch. The cause value should
> only be decremented by one for VS mode interrupts. In case if hypervisor has
> delegated S mode interrupts then we should not decrement cause for those
> interrupts.
>
> Regards,
> Rajnesh
>
>
> On Sun, Feb 23, 2020 at 7:41 PM Jose Martins <mailto:josemartins90@gmail.com> wrote:
>>
>> Hello rajnesh,
>>
>> I had already submitted almost this exact patch a few weeks ago.
>>
>> Jose
>>
>> On Sun, 23 Feb 2020 at 13:51, <mailto:rajnesh.kanwal49@gmail.com> wrote:
>> >
>> > From: Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com>
>> >
>> > Currently riscv_cpu_local_irq_pending is used to find out pending
>> > interrupt and VS mode interrupts are being shifted to represent
>> > S mode interrupts in this function. So when the cause returned by
>> > this function is passed to riscv_cpu_do_interrupt to actually
>> > forward the interrupt, the VS mode forwarding check does not work
>> > as intended and interrupt is actually forwarded to hypervisor. This
>> > patch fixes this issue.
>> >
>> > Signed-off-by: Rajnesh Kanwal <mailto:rajnesh.kanwal49@gmail.com>
>> > ---
>> >  target/riscv/cpu_helper.c | 9 ++++++++-
>> >  1 file changed, 8 insertions(+), 1 deletion(-)
>> >
>> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> > index b9e90dfd9a..59535ecba6 100644
>> > --- a/target/riscv/cpu_helper.c
>> > +++ b/target/riscv/cpu_helper.c
>> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
>> >      target_ulong pending = env->mip & env->mie &
>> >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
>> >      target_ulong vspending = (env->mip & env->mie &
>> > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
>> > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
>> >
>> >      target_ulong mie    = env->priv < PRV_M ||
>> >                            (env->priv == PRV_M && mstatus_mie);
>> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> >
>> >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
>> >                  !force_hs_execp) {
>> > +                /*
>> > +                 * See if we need to adjust cause. Yes if its VS mode interrupt
>> > +                 * no if hypervisor has delegated one of hs mode's interrupt
>> > +                 */
>> > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
>> > +                    cause == IRQ_VS_EXT)
>> > +                    cause = cause - 1;
>> >                  /* Trap to VS mode */
>> >              } else if (riscv_cpu_virt_enabled(env)) {
>> >                  /* Trap into HS mode, from virt */
>> > --
>> > 2.17.1
>> >
>> >
Alistair Francis Feb. 24, 2020, 6:59 p.m. UTC | #6 
On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote:
>
> Hello rajnesh,
>
> I had already submitted almost this exact patch a few weeks ago.

To QEMU? I don't see the patch.

Alistair

>
> Jose
>
> On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
> >
> > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> >
> > Currently riscv_cpu_local_irq_pending is used to find out pending
> > interrupt and VS mode interrupts are being shifted to represent
> > S mode interrupts in this function. So when the cause returned by
> > this function is passed to riscv_cpu_do_interrupt to actually
> > forward the interrupt, the VS mode forwarding check does not work
> > as intended and interrupt is actually forwarded to hypervisor. This
> > patch fixes this issue.
> >
> > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> > ---
> >  target/riscv/cpu_helper.c | 9 ++++++++-
> >  1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > index b9e90dfd9a..59535ecba6 100644
> > --- a/target/riscv/cpu_helper.c
> > +++ b/target/riscv/cpu_helper.c
> > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
> >      target_ulong pending = env->mip & env->mie &
> >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
> >      target_ulong vspending = (env->mip & env->mie &
> > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
> > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
> >
> >      target_ulong mie    = env->priv < PRV_M ||
> >                            (env->priv == PRV_M && mstatus_mie);
> > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> >
> >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
> >                  !force_hs_execp) {
> > +                /*
> > +                 * See if we need to adjust cause. Yes if its VS mode interrupt
> > +                 * no if hypervisor has delegated one of hs mode's interrupt
> > +                 */
> > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> > +                    cause == IRQ_VS_EXT)
> > +                    cause = cause - 1;
> >                  /* Trap to VS mode */
> >              } else if (riscv_cpu_virt_enabled(env)) {
> >                  /* Trap into HS mode, from virt */
> > --
> > 2.17.1
> >
> >
>
Rajnesh Kanwal Feb. 26, 2020, 8:52 a.m. UTC | #7 
Here is the link to the patch
https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html

-Rajnesh

On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com>
wrote:

> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com>
> wrote:
> >
> > Hello rajnesh,
> >
> > I had already submitted almost this exact patch a few weeks ago.
>
> To QEMU? I don't see the patch.
>
> Alistair
>
> >
> > Jose
> >
> > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
> > >
> > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> > >
> > > Currently riscv_cpu_local_irq_pending is used to find out pending
> > > interrupt and VS mode interrupts are being shifted to represent
> > > S mode interrupts in this function. So when the cause returned by
> > > this function is passed to riscv_cpu_do_interrupt to actually
> > > forward the interrupt, the VS mode forwarding check does not work
> > > as intended and interrupt is actually forwarded to hypervisor. This
> > > patch fixes this issue.
> > >
> > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
> > > ---
> > >  target/riscv/cpu_helper.c | 9 ++++++++-
> > >  1 file changed, 8 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> > > index b9e90dfd9a..59535ecba6 100644
> > > --- a/target/riscv/cpu_helper.c
> > > +++ b/target/riscv/cpu_helper.c
> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState
> *env)
> > >      target_ulong pending = env->mip & env->mie &
> > >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
> > >      target_ulong vspending = (env->mip & env->mie &
> > > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >>
> 1;
> > > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
> > >
> > >      target_ulong mie    = env->priv < PRV_M ||
> > >                            (env->priv == PRV_M && mstatus_mie);
> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> > >
> > >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) &
> 1) &&
> > >                  !force_hs_execp) {
> > > +                /*
> > > +                 * See if we need to adjust cause. Yes if its VS mode
> interrupt
> > > +                 * no if hypervisor has delegated one of hs mode's
> interrupt
> > > +                 */
> > > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
> > > +                    cause == IRQ_VS_EXT)
> > > +                    cause = cause - 1;
> > >                  /* Trap to VS mode */
> > >              } else if (riscv_cpu_virt_enabled(env)) {
> > >                  /* Trap into HS mode, from virt */
> > > --
> > > 2.17.1
> > >
> > >
> >
>
Alistair Francis Feb. 26, 2020, 5:55 p.m. UTC | #8 
On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal
<rajnesh.kanwal49@gmail.com> wrote:
>
> Here is the link to the patch
> https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html

Ah, it doesn't look like it made it to the QEMU-devel list. Can you
re-send it to QEMU-devel?

Alistair

>
> -Rajnesh
>
> On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote:
>>
>> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote:
>> >
>> > Hello rajnesh,
>> >
>> > I had already submitted almost this exact patch a few weeks ago.
>>
>> To QEMU? I don't see the patch.
>>
>> Alistair
>>
>> >
>> > Jose
>> >
>> > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
>> > >
>> > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>> > >
>> > > Currently riscv_cpu_local_irq_pending is used to find out pending
>> > > interrupt and VS mode interrupts are being shifted to represent
>> > > S mode interrupts in this function. So when the cause returned by
>> > > this function is passed to riscv_cpu_do_interrupt to actually
>> > > forward the interrupt, the VS mode forwarding check does not work
>> > > as intended and interrupt is actually forwarded to hypervisor. This
>> > > patch fixes this issue.
>> > >
>> > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>> > > ---
>> > >  target/riscv/cpu_helper.c | 9 ++++++++-
>> > >  1 file changed, 8 insertions(+), 1 deletion(-)
>> > >
>> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>> > > index b9e90dfd9a..59535ecba6 100644
>> > > --- a/target/riscv/cpu_helper.c
>> > > +++ b/target/riscv/cpu_helper.c
>> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
>> > >      target_ulong pending = env->mip & env->mie &
>> > >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
>> > >      target_ulong vspending = (env->mip & env->mie &
>> > > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
>> > > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
>> > >
>> > >      target_ulong mie    = env->priv < PRV_M ||
>> > >                            (env->priv == PRV_M && mstatus_mie);
>> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>> > >
>> > >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
>> > >                  !force_hs_execp) {
>> > > +                /*
>> > > +                 * See if we need to adjust cause. Yes if its VS mode interrupt
>> > > +                 * no if hypervisor has delegated one of hs mode's interrupt
>> > > +                 */
>> > > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
>> > > +                    cause == IRQ_VS_EXT)
>> > > +                    cause = cause - 1;
>> > >                  /* Trap to VS mode */
>> > >              } else if (riscv_cpu_virt_enabled(env)) {
>> > >                  /* Trap into HS mode, from virt */
>> > > --
>> > > 2.17.1
>> > >
>> > >
>> >
Palmer Dabbelt March 6, 2020, 5:31 p.m. UTC | #9 
On Wed, 26 Feb 2020 09:55:34 PST (-0800), alistair23@gmail.com wrote:
> On Wed, Feb 26, 2020 at 12:54 AM Rajnesh Kanwal
> <rajnesh.kanwal49@gmail.com> wrote:
>>
>> Here is the link to the patch
>> https://lists.nongnu.org/archive/html/qemu-riscv/2020-01/msg00191.html
>
> Ah, it doesn't look like it made it to the QEMU-devel list. Can you
> re-send it to QEMU-devel?

I can't find the older patch in my inbox, so I'm just taking this one.

>
> Alistair
>
>>
>> -Rajnesh
>>
>> On Tue, Feb 25, 2020 at 12:06 AM Alistair Francis <alistair23@gmail.com> wrote:
>>>
>>> On Sun, Feb 23, 2020 at 11:23 AM Jose Martins <josemartins90@gmail.com> wrote:
>>> >
>>> > Hello rajnesh,
>>> >
>>> > I had already submitted almost this exact patch a few weeks ago.
>>>
>>> To QEMU? I don't see the patch.
>>>
>>> Alistair
>>>
>>> >
>>> > Jose
>>> >
>>> > On Sun, 23 Feb 2020 at 13:51, <rajnesh.kanwal49@gmail.com> wrote:
>>> > >
>>> > > From: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>>> > >
>>> > > Currently riscv_cpu_local_irq_pending is used to find out pending
>>> > > interrupt and VS mode interrupts are being shifted to represent
>>> > > S mode interrupts in this function. So when the cause returned by
>>> > > this function is passed to riscv_cpu_do_interrupt to actually
>>> > > forward the interrupt, the VS mode forwarding check does not work
>>> > > as intended and interrupt is actually forwarded to hypervisor. This
>>> > > patch fixes this issue.
>>> > >
>>> > > Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
>>> > > ---
>>> > >  target/riscv/cpu_helper.c | 9 ++++++++-
>>> > >  1 file changed, 8 insertions(+), 1 deletion(-)
>>> > >
>>> > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
>>> > > index b9e90dfd9a..59535ecba6 100644
>>> > > --- a/target/riscv/cpu_helper.c
>>> > > +++ b/target/riscv/cpu_helper.c
>>> > > @@ -46,7 +46,7 @@ static int riscv_cpu_local_irq_pending(CPURISCVState *env)
>>> > >      target_ulong pending = env->mip & env->mie &
>>> > >                                 ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
>>> > >      target_ulong vspending = (env->mip & env->mie &
>>> > > -                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
>>> > > +                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
>>> > >
>>> > >      target_ulong mie    = env->priv < PRV_M ||
>>> > >                            (env->priv == PRV_M && mstatus_mie);
>>> > > @@ -900,6 +900,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
>>> > >
>>> > >              if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
>>> > >                  !force_hs_execp) {
>>> > > +                /*
>>> > > +                 * See if we need to adjust cause. Yes if its VS mode interrupt
>>> > > +                 * no if hypervisor has delegated one of hs mode's interrupt
>>> > > +                 */
>>> > > +                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
>>> > > +                    cause == IRQ_VS_EXT)
>>> > > +                    cause = cause - 1;
>>> > >                  /* Trap to VS mode */
>>> > >              } else if (riscv_cpu_virt_enabled(env)) {
>>> > >                  /* Trap into HS mode, from virt */
>>> > > --
>>> > > 2.17.1
>>> > >
>>> > >
>>> >
diff mbox series

Patch

diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index b9e90dfd9a..59535ecba6 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -46,7 +46,7 @@  static int riscv_cpu_local_irq_pending(CPURISCVState *env)
     target_ulong pending = env->mip & env->mie &
                                ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP);
     target_ulong vspending = (env->mip & env->mie &
-                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)) >> 1;
+                              (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP));
 
     target_ulong mie    = env->priv < PRV_M ||
                           (env->priv == PRV_M && mstatus_mie);
@@ -900,6 +900,13 @@  void riscv_cpu_do_interrupt(CPUState *cs)
 
             if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
                 !force_hs_execp) {
+                /*
+                 * See if we need to adjust cause. Yes if its VS mode interrupt
+                 * no if hypervisor has delegated one of hs mode's interrupt
+                 */
+                if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
+                    cause == IRQ_VS_EXT)
+                    cause = cause - 1;
                 /* Trap to VS mode */
             } else if (riscv_cpu_virt_enabled(env)) {
                 /* Trap into HS mode, from virt */