Show patches with: Submitter = Ivan Klokov       |    State = Action Required       |    Archived = No       |   17 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[1/1] target/riscv: pmp: Ignore writes when RW=01 and MML=0 [1/1] target/riscv: pmp: Ignore writes when RW=01 and MML=0 - 1 2 - --- 2023-12-20 Ivan Klokov New
[1/1] target/riscv: Clear vstart_qe_zero flag [1/1] target/riscv: Clear vstart_qe_zero flag - - - - --- 2023-12-14 Ivan Klokov New
[1/1] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 [1/1] target/riscv/pmp: Use hwaddr instead of target_ulong for RV32 - - 1 - --- 2023-11-23 Ivan Klokov New
[v2,2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior Fix mmu translation with H extension - 1 2 - --- 2023-11-21 Ivan Klokov New
[v2,1/2] target/riscv/cpu_helper.c: Invalid exception on MMU translation stage Fix mmu translation with H extension - 1 2 - --- 2023-11-21 Ivan Klokov New
[2/2] target/riscv/cpu_helper.c: Fix mxr bit behavior Fix mmu translation with H extension - 1 1 - --- 2023-11-20 Ivan Klokov New
[1/2] target/riscv/cpu_helper.c: Invalid exception on MMU translation stage Fix mmu translation with H extension - 1 2 - --- 2023-11-20 Ivan Klokov New
[v5,1/1] target/riscv: Add RVV registers to log [v5,1/1] target/riscv: Add RVV registers to log - - 2 - --- 2023-06-29 Ivan Klokov New
[v4,1/1] target/riscv: Add RVV registers to log [v4,1/1] target/riscv: Add RVV registers to log - - - - --- 2023-06-22 Ivan Klokov New
hw/intc/riscv_aplic: Zero init APLIC internal state hw/intc/riscv_aplic: Zero init APLIC internal state - - 2 - --- 2023-04-13 Ivan Klokov New
[v3,2/2] target/riscv: Add RVV registers to log Support for print to log vector extension registers - - 1 - --- 2023-04-10 Ivan Klokov New
[v3,1/2] util/log: Add vector registers to log Support for print to log vector extension registers - - 1 - --- 2023-04-10 Ivan Klokov New
[v2] target/riscv: Add RVV registers to log [v2] target/riscv: Add RVV registers to log - - - - --- 2023-03-09 Ivan Klokov New
Fix slli_uw decoding Fix slli_uw decoding 1 - 1 - --- 2023-02-27 Ivan Klokov New
disas/riscv Fix ctzw disassemble disas/riscv Fix ctzw disassemble - 1 2 - --- 2023-02-17 Ivan Klokov New
disas/riscv Fix ctzw disassemble disas/riscv Fix ctzw disassemble - 1 - - --- 2023-02-17 Ivan Klokov New
target/riscv: Add RVV registers to log target/riscv: Add RVV registers to log - - - - --- 2023-02-01 Ivan Klokov New