Show patches with: Submitter = Idan Horowitz       |    State = Action Required       |    Archived = No       |   11 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
target/arm: Fix MTE access checks for disabled SEL2 target/arm: Fix MTE access checks for disabled SEL2 - - 1 - --- 2022-03-28 Idan Horowitz New
[3/3] target/arm: Determine final stage 2 output PA space based on original IPA Bug fixes related to secure 2 stage translation - - 1 - --- 2022-03-27 Idan Horowitz New
[2/3] target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk Bug fixes related to secure 2 stage translation - - 1 - --- 2022-03-27 Idan Horowitz New
[1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space Bug fixes related to secure 2 stage translation - - 1 - --- 2022-03-27 Idan Horowitz New
target/riscv: Exit current TB after an sfence.vma target/riscv: Exit current TB after an sfence.vma - - 2 - --- 2022-03-15 Idan Horowitz New
[2/2] qemu-timer: Skip empty timer lists before locking in qemu_clock_deadline_ns_all [1/2] softmmu/cpus: Check if the cpu work list is empty atomically - - 1 - --- 2022-01-14 Idan Horowitz New
[1/2] softmmu/cpus: Check if the cpu work list is empty atomically [1/2] softmmu/cpus: Check if the cpu work list is empty atomically - - 1 - --- 2022-01-14 Idan Horowitz New
target/arm: Allow only specific instructions based on the SCTLR_EL1.UCI bit target/arm: Allow only specific instructions based on the SCTLR_EL1.UCI bit - - - - --- 2022-01-14 Idan Horowitz New
[2/2] target/arm: Bail out early on 0-length tlb range invalidate [1/2] accel/tcg: Optimize jump cache flush during tlb range flush - - 1 - --- 2022-01-10 Idan Horowitz New
[1/2] accel/tcg: Optimize jump cache flush during tlb range flush [1/2] accel/tcg: Optimize jump cache flush during tlb range flush - - 1 - --- 2022-01-10 Idan Horowitz New
target/arm: Add missing FEAT_TLBIOS instructions target/arm: Add missing FEAT_TLBIOS instructions - 1 1 - --- 2021-12-31 Idan Horowitz New