Show patches with: Archived = No       |   430996 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v2,4/4] riscv: Keep the CPU init routine names consistent [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,3/4] riscv: Generalize CPU init routine for the imacu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,2/4] riscv: Generalize CPU init routine for the gcsu CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[v2,1/4] riscv: Generalize CPU init routine for the base CPU [v2,1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-11 Bin Meng New
[15/15] hw/riscv: sifive_u: Add a dummy DDR memory controller device hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[14/15] hw/riscv: sifive_u: Sort the SoC memmap table entries hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[13/15] hw/riscv: sifive_u: Support different boot source per MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[12/15] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - - - --- 2020-06-08 Bin Meng New
[11/15] hw/riscv: sifive_u: Add a new property msel for MSEL pin state hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[10/15] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[09/15] hw/riscv: sifive_u: Add reset functionality hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[08/15] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[07/15] hw/riscv: sifive_u: Hook a GPIO controller hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[06/15] hw/riscv: sifive_gpio: Add a new 'ngpio' property hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[05/15] hw/riscv: sifive_gpio: Clean up the codes hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[04/15] hw/riscv: sifive_u: Generate device tree node for OTP hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[03/15] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[02/15] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[01/15] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions hw/riscv: sifive_u: Add GPIO and Mode Select (MSEL[3:0]) support - - 1 - --- 2020-06-08 Bin Meng New
[4/4] riscv: Keep the CPU init routine names consistent [1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-05 Bin Meng Superseded
[3/4] riscv: Generalize CPU init routine for the imacu CPU [1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-05 Bin Meng Superseded
[2/4] riscv: Generalize CPU init routine for the gcsu CPU [1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-05 Bin Meng Superseded
[1/4] riscv: Generalize CPU init routine for the base CPU [1/4] riscv: Generalize CPU init routine for the base CPU - - 1 - --- 2020-06-05 Bin Meng Superseded
[2/2] hw/riscv: virt: Remove the riscv_ prefix of the machine* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions [1/2] hw/riscv: sifive_u: Remove the riscv_ prefix of the soc* functions - - 2 - --- 2020-05-21 Bin Meng New
[5/5] riscv: Suppress the error report for QEMU testing with riscv_find_firmware() riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[4/5] riscv/spike: Change the default bios to use generic platform image riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[3/5] riscv: Use pre-built bios image of generic platform for virt & sifive_u riscv: Switch to use generic platform of opensbi bios images - - 2 - --- 2020-05-01 Bin Meng New
[2/5] gitlab-ci/opensbi: Update GitLab CI to build generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
[1/5] roms/opensbi: Update to support building bios images for generic platform riscv: Switch to use generic platform of opensbi bios images - - 1 - --- 2020-05-01 Bin Meng New
riscv/spike: Change the default bios to use plain binary image riscv/spike: Change the default bios to use plain binary image - - - - --- 2020-05-01 Bin Meng New
riscv: Change the default behavior if no -bios option is specified riscv: Change the default behavior if no -bios option is specified - - 1 - --- 2020-05-01 Bin Meng New
roms: opensbi: Upgrade from v0.6 to v0.7 roms: opensbi: Upgrade from v0.6 to v0.7 - - 1 - --- 2020-04-20 Bin Meng New
hw/riscv: Generate correct "mmu-type" for 32-bit machines hw/riscv: Generate correct "mmu-type" for 32-bit machines - - 1 - --- 2020-03-07 Bin Meng New
[v2,4/4] gitlab-ci.yml: Add jobs to build OpenSBI firmware binaries riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image 1 - - - --- 2020-02-24 Bin Meng New
[v2,3/4] riscv: sifive_u: Update BIOS_FILENAME for 32-bit riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[v2,2/4] roms: opensbi: Add 32-bit firmware image for sifive_u machine riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[v2,1/4] roms: opensbi: Upgrade from v0.5 to v0.6 riscv: Upgrade OpenSBI to v0.6 and add 32-bit sifive_u bios image - - 1 - --- 2020-02-24 Bin Meng New
[2/2] riscv: sifive_u: Update BIOS_FILENAME for 32-bit [1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u - - 1 - --- 2020-02-20 Bin Meng Superseded
[1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u [1/2] riscv: roms: Add 32-bit OpenSBI firmware image for sifive_u - - - - --- 2020-02-20 Bin Meng Superseded
[v2] riscv: sifive_u: Add a "serial" property for board serial number [v2] riscv: sifive_u: Add a "serial" property for board serial number - - 1 - --- 2020-02-16 Bin Meng New
riscv: virt: Allow PCI address 0 riscv: virt: Allow PCI address 0 - - 1 - --- 2019-11-22 Bin Meng New
riscv: sifive_u: Add a "serial" property for board serial number riscv: sifive_u: Add a "serial" property for board serial number - - 2 - --- 2019-11-16 Bin Meng Superseded
[v2,2/2] riscv: sifive_u: Add ethernet0 to the aliases node [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 2 - --- 2019-09-21 Bin Meng New
[v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes [v2,1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes - - 1 - --- 2019-09-21 Bin Meng New
riscv: Skip checking CSR privilege level in debugger mode riscv: Skip checking CSR privilege level in debugger mode - - 1 - --- 2019-09-20 Bin Meng New
[2/2] riscv: sifive_u: Add ethernet0 to the aliases node [1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes - - 1 - --- 2019-09-20 Bin Meng Superseded
[1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes [1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes - - 1 - --- 2019-09-20 Bin Meng Superseded
[v8,32/32] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,30/32] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,29/32] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,28/32] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,27/32] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,26/32] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,25/32] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-09-06 Bin Meng New
[v8,24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,23/32] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,21/32] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,20/32] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,18/32] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,16/32] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,14/32] riscv: sifive_e: Drop sifive_mmio_emulate() riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,13/32] riscv: sifive_e: prci: Update the PRCI register block size riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-09-06 Bin Meng New
[v8,11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h} riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,10/32] riscv: sifive_u: Remove the unnecessary include of prci header riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,06/32] riscv: hw: Change create_fdt() to return void riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 3 - --- 2019-09-06 Bin Meng New
[v8,05/32] riscv: hw: Remove not needed PLIC properties in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-06 Bin Meng New
[v8,04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,03/32] riscv: hw: Remove superfluous "linux, phandle" property riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,02/32] riscv: sifive_test: Add reset functionality riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-06 Bin Meng New
[v8,01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion [v8,01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion - 1 1 - --- 2019-09-06 Bin Meng New
riscv: hw: Remove duplicated "hw/hw.h" inclusion riscv: hw: Remove duplicated "hw/hw.h" inclusion - 1 - - --- 2019-09-06 Bin Meng Superseded
[v2] riscv: sifive_test: Add reset functionality [v2] riscv: sifive_test: Add reset functionality - - 1 - --- 2019-09-05 Bin Meng New
[v7,30/30] riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,28/30] riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,27/30] riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,26/30] riscv: sifive: Implement a model for SiFive FU540 OTP riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,25/30] riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,24/30] riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,23/30] riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Improve the emulation fidelity of sifive_u machine 1 - 2 - --- 2019-09-01 Bin Meng Superseded
[v7,22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,21/30] riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,19/30] riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,18/30] riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,16/30] riscv: sifive_u: Set the minimum number of cpus to 2 riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,14/30] riscv: hart: Extract hart realize to a separate routine riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
[v7,13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 2 - --- 2019-09-01 Bin Meng Superseded
[v7,12/30] riscv: sifive_e: Drop sifive_mmio_emulate() riscv: sifive_u: Improve the emulation fidelity of sifive_u machine - - 1 - --- 2019-09-01 Bin Meng Superseded
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