Show patches with: Series = Add RISC-V vector cryptographic instruction set support       |    State = Action Required       |    Archived = No       |   15 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v6,15/15] target/riscv: Add Zvksed ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,14/15] crypto: Add SM4 constant parameter CK Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,13/15] crypto: Create sm4_subword Add RISC-V vector cryptographic instruction set support - - 2 - --- 2023-06-27 Max Chou New
[v6,12/15] target/riscv: Add Zvkg ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,11/15] target/riscv: Add Zvksh ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,10/15] target/riscv: Add Zvknh ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,09/15] target/riscv: Add Zvkned ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,08/15] target/riscv: Add Zvbb ISA extension support Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,07/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,06/15] target/riscv: Refactor translation of vector-widening instruction Add RISC-V vector cryptographic instruction set support - - 2 - --- 2023-06-27 Max Chou New
[v6,05/15] target/riscv: Move vector translation checks Add RISC-V vector cryptographic instruction set support - - 2 - --- 2023-06-27 Max Chou New
[v6,04/15] target/riscv: Add Zvbc ISA extension support Add RISC-V vector cryptographic instruction set support - - - - --- 2023-06-27 Max Chou New
[v6,03/15] target/riscv: Remove redundant "cpu_vl == 0" checks Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New
[v6,02/15] target/riscv: Refactor vector-vector translation macro Add RISC-V vector cryptographic instruction set support - - 3 - --- 2023-06-27 Max Chou New
[v6,01/15] target/riscv: Refactor some of the generic vector functionality Add RISC-V vector cryptographic instruction set support - - 1 - --- 2023-06-27 Max Chou New