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[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
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Apply
Patch
Series
A/F/R/T
S/W/F
Date
Submitter
Delegate
State
[PULL,32/32] hw/riscv: sifive_u: Add a dummy DDR memory controller device
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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-
2020-06-19
Alistair Francis
New
[PULL,31/32] hw/riscv: sifive_u: Sort the SoC memmap table entries
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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-
2020-06-19
Alistair Francis
New
[PULL,30/32] hw/riscv: sifive_u: Support different boot source per MSEL pin state
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,29/32] hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,28/32] target/riscv: Rename IBEX CPU init routine
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,27/32] hw/riscv: sifive_u: Add a new property msel for MSEL pin state
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,26/32] hw/riscv: sifive_u: Rename serial property get/set functions to a generic name
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,25/32] hw/riscv: sifive_u: Add reset functionality
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,24/32] hw/riscv: sifive_gpio: Do not blindly trigger output IRQs
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,23/32] hw/riscv: sifive_u: Hook a GPIO controller
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,22/32] hw/riscv: sifive_gpio: Add a new 'ngpio' property
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,21/32] hw/riscv: sifive_gpio: Clean up the codes
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,20/32] hw/riscv: sifive_u: Generate device tree node for OTP
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,19/32] hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,18/32] hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
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2020-06-19
Alistair Francis
New
[PULL,17/32] hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,16/32] target/riscv: Use a smaller guess size for no-MMU PMP
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,15/32] riscv/opentitan: Connect the UART device
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 2 -
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2020-06-19
Alistair Francis
New
[PULL,14/32] riscv/opentitan: Connect the PLIC device
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 2 -
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2020-06-19
Alistair Francis
New
[PULL,13/32] hw/intc: Initial commit of lowRISC Ibex PLIC
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,12/32] hw/char: Initial commit of Ibex UART
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
-
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2020-06-19
Alistair Francis
New
[PULL,11/32] riscv/opentitan: Fix the ROM size
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - - -
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2020-06-19
Alistair Francis
New
[PULL,10/32] target/riscv: Implement checks for hfence
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,09/32] target/riscv: Move the hfence instructions to the rvh decode
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,08/32] target/riscv: Report errors validating 2nd-stage PTEs
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,07/32] target/riscv: Set access as data_load when validating stage-2 PTEs
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,06/32] riscv: Keep the CPU init routine names consistent
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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-
2020-06-19
Alistair Francis
New
[PULL,05/32] riscv: Generalize CPU init routine for the imacu CPU
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,04/32] riscv: Generalize CPU init routine for the gcsu CPU
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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2020-06-19
Alistair Francis
New
[PULL,03/32] riscv: Generalize CPU init routine for the base CPU
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 1 -
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-
2020-06-19
Alistair Francis
New
[PULL,02/32] sifive_e: Support the revB machine
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - - -
-
-
-
2020-06-19
Alistair Francis
New
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
[PULL,01/32] riscv: Add helper to make NaN-boxing for FP register
- - 2 -
-
-
-
2020-06-19
Alistair Francis
New