Show patches with: State = Action Required       |    Archived = No       |   427569 patches
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Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v8,7/7] net/vmnet: update MAINTAINERS list Add vmnet.framework based network backend - - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v8,6/7] net/vmnet: update qemu-options.hx Add vmnet.framework based network backend - - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v8,5/7] net/vmnet: implement bridged mode (vmnet-bridged) Add vmnet.framework based network backend - - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v8,4/7] net/vmnet: implement host mode (vmnet-host) Add vmnet.framework based network backend - - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v8,3/7] net/vmnet: implement shared mode (vmnet-shared) Add vmnet.framework based network backend - - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v8,2/7] net/vmnet: add vmnet backends to qapi/net Add vmnet.framework based network backend 1 - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v8,1/7] net/vmnet: add vmnet dependency and customizable option Add vmnet.framework based network backend - - - - --- 2021-12-11 Vladislav Yaroshchuk New
[v5,23/23] hw/riscv: virt: Increase maximum number of allowed CPUs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,22/23] docs/system: riscv: Document AIA options for virt machine [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,21/23] hw/riscv: virt: Add optional AIA IMSIC support to virt machine [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,20/23] hw/intc: Add RISC-V AIA IMSIC device emulation [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,19/23] hw/riscv: virt: Add optional AIA APLIC support to virt machine [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,18/23] hw/intc: Add RISC-V AIA APLIC device emulation [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,17/23] target/riscv: Allow users to force enable AIA CSRs in HART [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,16/23] hw/riscv: virt: Use AIA INTC compatible string when available [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,15/23] target/riscv: Implement AIA IMSIC interface CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,14/23] target/riscv: Implement AIA xiselect and xireg CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - - - --- 2021-12-11 Anup Patel New
[v5,12/23] target/riscv: Implement AIA interrupt filtering CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,09/23] target/riscv: Implement AIA local interrupt priorities [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,07/23] target/riscv: Add defines for AIA CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,06/23] target/riscv: Add AIA cpu feature [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 2 - --- 2021-12-11 Anup Patel New
[v5,05/23] target/riscv: Allow setting CPU feature from machine/device emulation [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 2 - --- 2021-12-11 Anup Patel New
[v5,04/23] target/riscv: Improve delivery of guest external interrupts [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,03/23] target/riscv: Implement hgeie and hgeip CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - - 1 - --- 2021-12-11 Anup Patel New
[v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode [v5,01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode - 1 2 - --- 2021-12-11 Anup Patel New
[2/2] linux-user: call set/getscheduler set/getparam directly linux-user: fixes for sched_ syscalls - - - - --- 2021-12-11 Tonis Tiigi New
[1/2] linux-user: add sched_getattr support linux-user: fixes for sched_ syscalls - - - - --- 2021-12-11 Tonis Tiigi New
COLO: Move some trace code behind qemu_mutex_unlock_iothread() COLO: Move some trace code behind qemu_mutex_unlock_iothread() - - - - --- 2021-12-10 Lei Rao New
iotests/testrunner.py: refactor test_field_width iotests/testrunner.py: refactor test_field_width - - 1 - --- 2021-12-10 Vladimir Sementsov-Ogievskiy New
xen-hvm: Allow disabling buffer_io_timer xen-hvm: Allow disabling buffer_io_timer - - 1 - --- 2021-12-10 Jason Andryuk New
[v7,8/8] tests/acpi: add expected blob for VIOT test on virt machine virtio-iommu: Add ACPI support (Arm part + tests) 1 - 1 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,7/8] tests/acpi: add expected blobs for VIOT test on q35 machine virtio-iommu: Add ACPI support (Arm part + tests) - - 1 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,6/8] tests/acpi: add test case for VIOT virtio-iommu: Add ACPI support (Arm part + tests) - - 2 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,5/8] tests/acpi: allow updates of VIOT expected data files virtio-iommu: Add ACPI support (Arm part + tests) 1 - 1 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,4/8] hw/arm/virt: Use object_property_set instead of qdev_prop_set virtio-iommu: Add ACPI support (Arm part + tests) - - 2 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,3/8] hw/arm/virt: Reject instantiation of multiple IOMMUs virtio-iommu: Add ACPI support (Arm part + tests) - 1 2 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,2/8] hw/arm/virt: Remove device tree restriction for virtio-iommu virtio-iommu: Add ACPI support (Arm part + tests) 1 - 1 - --- 2021-12-10 Jean-Philippe Brucker New
[v7,1/8] hw/arm/virt-acpi-build: Add VIOT table for virtio-iommu virtio-iommu: Add ACPI support (Arm part + tests) 1 - 1 - --- 2021-12-10 Jean-Philippe Brucker New
[2/2] scsi/utils: pass host_status = SCSI_HOST_ERROR to guest kernel scsi: to fix issue on passing host_status to the guest kernel - - - - --- 2021-12-10 Dongli Zhang New
[1/2] scsi/scsi_bus: use host_status as parameter for scsi_sense_from_host_status() scsi: to fix issue on passing host_status to the guest kernel - 1 - - --- 2021-12-10 Dongli Zhang New
[4/4] target/ppc: move xscvqpdp to decodetree target/ppc: Fix VSX instructions register access - - 1 - --- 2021-12-10 Víctor Colombo New
[3/4] target/ppc: fix xscvqpdp register access target/ppc: Fix VSX instructions register access - - 1 - --- 2021-12-10 Víctor Colombo New
[2/4] target/ppc: Move xs{max,min}[cj]dp to decodetree target/ppc: Fix VSX instructions register access - - 1 - --- 2021-12-10 Víctor Colombo New
[1/4] target/ppc: Fix xs{max,min}[cj]dp to use VSX registers target/ppc: Fix VSX instructions register access - - 1 - --- 2021-12-10 Víctor Colombo New
configure: remove DIRS configure: remove DIRS - - 2 1 --- 2021-12-10 Paolo Bonzini New
tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUX tests/tcg: use CONFIG_LINUX_USER, not CONFIG_LINUX - - - - --- 2021-12-10 Paolo Bonzini New
configure: remove dead variables configure: remove dead variables - - 2 - --- 2021-12-10 Paolo Bonzini New
[v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU) [v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU) - - 2 - --- 2021-12-10 Troy Lee New
uas: add missing return uas: add missing return - 1 1 - --- 2021-12-10 Gerd Hoffmann New
[v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU) [v1] Add dummy Aspeed AST2600 Display Port MCU (DPMCU) - - - - --- 2021-12-10 Troy Lee New
[v11,77/77] target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,76/77] target/riscv: rvv-1.0: update opivv_vadc_check() comment support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,75/77] target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmorn.mm support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,74/77] target/riscv: rvv-1.0: add vector unit-stride mask load/store insns support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,73/77] target/riscv: rvv-1.0: add evl parameter to vext_ldst_us() support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,72/77] target/riscv: rvv-1.0: add vsetivli instruction support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,71/77] target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11 support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,70/77] target/riscv: rvv-1.0: floating-point reciprocal estimate instruction support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,69/77] target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruction support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,68/77] target/riscv: gdb: support vector registers for rv64 & rv32 support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,67/77] target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,66/77] target/riscv: rvv-1.0: implement vstart CSR support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,65/77] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,64/77] target/riscv: rvv-1.0: narrowing floating-point/integer type-convert support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,63/77] target/riscv: add "set round to odd" rounding mode helper function support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,62/77] target/riscv: rvv-1.0: widening floating-point/integer type-convert support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,61/77] target/riscv: rvv-1.0: floating-point/integer type-convert instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,60/77] target/riscv: introduce floating-point rounding mode enum support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,59/77] target/riscv: rvv-1.0: floating-point min/max instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,58/77] target/riscv: rvv-1.0: remove integer extract instruction support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,57/77] target/riscv: rvv-1.0: remove vmford.vv and vmford.vf support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,56/77] target/riscv: rvv-1.0: remove widening saturating scaled multiply-add support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,55/77] target/riscv: rvv-1.0: single-width scaling shift instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,54/77] target/riscv: rvv-1.0: widening floating-point reduction instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,53/77] target/riscv: rvv-1.0: single-width floating-point reduction support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,52/77] target/riscv: rvv-1.0: narrowing fixed-point clip instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,51/77] target/riscv: rvv-1.0: floating-point slide instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,50/77] target/riscv: rvv-1.0: slide instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,49/77] target/riscv: rvv-1.0: mask-register logical instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,48/77] target/riscv: rvv-1.0: floating-point compare instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,47/77] target/riscv: rvv-1.0: integer comparison instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,46/77] target/riscv: rvv-1.0: single-width saturating add and subtract instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,45/77] target/riscv: rvv-1.0: widening integer multiply-add instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,44/77] target/riscv: rvv-1.0: narrowing integer right shift instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,43/77] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,42/77] target/riscv: rvv-1.0: single-width bit shift instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,41/77] target/riscv: rvv-1.0: single-width averaging add and subtract instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,40/77] target/riscv: rvv-1.0: integer extension instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,39/77] target/riscv: rvv-1.0: whole register move instructions support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,38/77] target/riscv: rvv-1.0: floating-point scalar move instructions support vector extension v1.0 1 - - - --- 2021-12-10 Frank Chang New
[v11,37/77] target/riscv: rvv-1.0: floating-point move instruction support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,36/77] target/riscv: rvv-1.0: integer scalar move instructions support vector extension v1.0 1 - 1 - --- 2021-12-10 Frank Chang New
[v11,35/77] target/riscv: rvv-1.0: register gather instructions support vector extension v1.0 - - 1 - --- 2021-12-10 Frank Chang New
[v11,34/77] target/riscv: rvv-1.0: allow load element with sign-extended support vector extension v1.0 - - 2 - --- 2021-12-10 Frank Chang New
[v11,33/77] target/riscv: rvv-1.0: element index instruction support vector extension v1.0 - - 2 - --- 2021-12-10 Frank Chang New
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