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[v1,0/4] RISC-V: SoCify the SiFive boards and connect the

Message ID cover.1525464177.git.alistair.francis@wdc.com
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Series RISC-V: SoCify the SiFive boards and connect the | expand

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Alistair Francis May 4, 2018, 8:12 p.m. UTC 
This series has two tasks:
 1. To conver the SiFive U and E machines into SoCs and boards
 2. To connect the Cadence GEM device to teh SiFive U board

After this series the SiFive E and U boards have their SoCs split into
seperate QEMU objects, which can be used on future boards if desired.

The RISC-V Virt and Spike boards have not been converted. They haven't
been converted as they aren't physical boards, so it doesn't make a
whole lot of sense to split them into an SoC and board. The only
disadvantage with this is that they now differ to the SiFive boards.

This series also connect the Cadence GEM device to the SiFive U board.
There are some interrupt line changes requried before this is possible.

Based-on: <1524699938-6764-1-git-send-email-mjc@sifive.com>

Alistair Francis (4):
  hw/riscv/sifive_u: Create a U54 SoC object
  hw/riscv/sifive_plic: Use gpios instead of irqs
  hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device
  hw/riscv/sifive_e: Create a E31 SoC object

 default-configs/riscv32-softmmu.mak |   1 +
 default-configs/riscv64-softmmu.mak |   1 +
 hw/riscv/sifive_e.c                 |  97 +++++++++++++++++------
 hw/riscv/sifive_plic.c              |   5 +-
 hw/riscv/sifive_u.c                 | 119 +++++++++++++++++++++++-----
 include/hw/riscv/sifive_e.h         |  16 +++-
 include/hw/riscv/sifive_u.h         |  22 ++++-
 7 files changed, 205 insertions(+), 56 deletions(-)