mbox series

[RFC,0/2] RISC-V: Add TSO extensions (Ztso/Ssdtso)

Message ID 20231113095605.1131443-1-christoph.muellner@vrull.eu
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Series RISC-V: Add TSO extensions (Ztso/Ssdtso) | expand

Message

Christoph Müllner Nov. 13, 2023, 9:56 a.m. UTC 
From: Christoph Müllner <christoph.muellner@vrull.eu>

This series picks up an earlier v2 Ztso patch from Palmer
and adds a second to support Ssdtso.

Palmer's v2 Ztso patch can be found here:
  https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/
This patch did not apply cleanly but the necessary changes were trivial.
There was a request to extend the commit message, which is part of the
posted patch of this series.  As this patch was reviewed a year ago,
I believe it could be merged.

The second patch adds support for dynamic TSO following the second
draft of the Ssdtso extension, which was published recently:
  https://lists.riscv.org/g/tech-arch-review/message/183
Note, that the Ssdtso specification is in development state
(i.e., not frozen or even ratified) which is also the reason
why I marked the series as RFC.

Relevant in this context might be also, that Richard's patch to improve
TCG's memory barrier selection depending on host and guest memory ordering
landed in June:
  https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/

Christoph Müllner (1):
  RISC-V: Add support for Ssdtso

Palmer Dabbelt (1):
  RISC-V: Add support for Ztso

 target/riscv/cpu.c                      |  4 ++++
 target/riscv/cpu_bits.h                 |  3 +++
 target/riscv/cpu_cfg.h                  |  2 ++
 target/riscv/csr.c                      |  9 ++++++---
 target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++---
 target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++--
 target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++
 target/riscv/translate.c                |  3 +++
 8 files changed, 60 insertions(+), 8 deletions(-)