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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id a11-20020a170906190b00b0098d2d219649sm3807321eje.174.2023.11.13.01.56.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Nov 2023 01:56:08 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , Palmer Dabbelt , Richard Henderson Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [RFC PATCH 0/2] RISC-V: Add TSO extensions (Ztso/Ssdtso) Date: Mon, 13 Nov 2023 10:56:01 +0100 Message-ID: <20231113095605.1131443-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Christoph Müllner This series picks up an earlier v2 Ztso patch from Palmer and adds a second to support Ssdtso. Palmer's v2 Ztso patch can be found here: https://patchwork.kernel.org/project/qemu-devel/patch/20220917072635.11616-1-palmer@rivosinc.com/ This patch did not apply cleanly but the necessary changes were trivial. There was a request to extend the commit message, which is part of the posted patch of this series. As this patch was reviewed a year ago, I believe it could be merged. The second patch adds support for dynamic TSO following the second draft of the Ssdtso extension, which was published recently: https://lists.riscv.org/g/tech-arch-review/message/183 Note, that the Ssdtso specification is in development state (i.e., not frozen or even ratified) which is also the reason why I marked the series as RFC. Relevant in this context might be also, that Richard's patch to improve TCG's memory barrier selection depending on host and guest memory ordering landed in June: https://lore.kernel.org/all/a313b36b-dcc1-f812-ccbd-afed1cbd523b@linaro.org/T/ Christoph Müllner (1): RISC-V: Add support for Ssdtso Palmer Dabbelt (1): RISC-V: Add support for Ztso target/riscv/cpu.c | 4 ++++ target/riscv/cpu_bits.h | 3 +++ target/riscv/cpu_cfg.h | 2 ++ target/riscv/csr.c | 9 ++++++--- target/riscv/insn_trans/trans_rva.c.inc | 11 ++++++++--- target/riscv/insn_trans/trans_rvi.c.inc | 16 ++++++++++++++-- target/riscv/insn_trans/trans_rvv.c.inc | 20 ++++++++++++++++++++ target/riscv/translate.c | 3 +++ 8 files changed, 60 insertions(+), 8 deletions(-)