| Message ID | 20210309072925.4314-1-frank.chang@sifive.com |
|---|---|
| Headers | show |
| Series | target/riscv: add RNMI support | expand |
On Tue, Mar 9, 2021 at 2:31 AM <frank.chang@sifive.com> wrote: > > From: Frank Chang <frank.chang@sifive.com> > > This patchset add suport of Resumable NMI (RNMI) in RISC-V. > > There are four new CSRs and one new instruction added to allow NMI to be > resumable in RISC-V, which are: > > ============================================================= > * mnscratch (0x350) > * mnepc (0x351) > * mncause (0x352) > * mnstatus (0x353) > ============================================================= > * mnret: To return from RNMI interrupt/exception handler. > ============================================================= > > RNMI also has higher priority than any other interrupts or exceptions > and cannot be disable by software. > > RNMI may be used to route to other devices such as Bus Error Unit or > Watchdog Timer in the future. > > The interrupt/exception trap handler addresses of RNMI are > implementation defined. > > The technical proposal of RNMI can be found: > https://lists.riscv.org/g/tech-privileged/message/421 > > The port is available here: > https://github.com/sifive/qemu/tree/nmi-upstream-v1 > > To enable RNMI feature, add cpu argument: 'rnmi=true' and specify > RNMI interrupt/exception handler addresses with 'rnmi_irqvec' and > 'rnmi_excpvec' arguments, e.g. > -cpu rv64,rnmi=true,rnmi_irqvec=0x2000,rnmi_excpvec=0x3000 Can you include details about the software you are using and how I can test this? Alistair > > Frank Chang (1): > target/riscv: add support of RNMI > > target/riscv/cpu.c | 40 +++++++++++++ > target/riscv/cpu.h | 16 ++++- > target/riscv/cpu_bits.h | 19 ++++++ > target/riscv/cpu_helper.c | 47 +++++++++++++-- > target/riscv/csr.c | 59 +++++++++++++++++++ > target/riscv/helper.h | 1 + > target/riscv/insn32.decode | 3 + > .../riscv/insn_trans/trans_privileged.c.inc | 13 ++++ > target/riscv/op_helper.c | 31 ++++++++++ > 9 files changed, 224 insertions(+), 5 deletions(-) > > -- > 2.17.1 > >
On Fri, Mar 19, 2021 at 9:30 PM Alistair Francis <alistair23@gmail.com> wrote: > On Tue, Mar 9, 2021 at 2:31 AM <frank.chang@sifive.com> wrote: > > > > From: Frank Chang <frank.chang@sifive.com> > > > > This patchset add suport of Resumable NMI (RNMI) in RISC-V. > > > > There are four new CSRs and one new instruction added to allow NMI to be > > resumable in RISC-V, which are: > > > > ============================================================= > > * mnscratch (0x350) > > * mnepc (0x351) > > * mncause (0x352) > > * mnstatus (0x353) > > ============================================================= > > * mnret: To return from RNMI interrupt/exception handler. > > ============================================================= > > > > RNMI also has higher priority than any other interrupts or exceptions > > and cannot be disable by software. > > > > RNMI may be used to route to other devices such as Bus Error Unit or > > Watchdog Timer in the future. > > > > The interrupt/exception trap handler addresses of RNMI are > > implementation defined. > > > > The technical proposal of RNMI can be found: > > https://lists.riscv.org/g/tech-privileged/message/421 > > > > The port is available here: > > https://github.com/sifive/qemu/tree/nmi-upstream-v1 > > > > To enable RNMI feature, add cpu argument: 'rnmi=true' and specify > > RNMI interrupt/exception handler addresses with 'rnmi_irqvec' and > > 'rnmi_excpvec' arguments, e.g. > > -cpu rv64,rnmi=true,rnmi_irqvec=0x2000,rnmi_excpvec=0x3000 > > Can you include details about the software you are using and how I can > test this? > > Alistair > Thanks, I'll include that in my next version patchset. Frank Chang > > > > > Frank Chang (1): > > target/riscv: add support of RNMI > > > > target/riscv/cpu.c | 40 +++++++++++++ > > target/riscv/cpu.h | 16 ++++- > > target/riscv/cpu_bits.h | 19 ++++++ > > target/riscv/cpu_helper.c | 47 +++++++++++++-- > > target/riscv/csr.c | 59 +++++++++++++++++++ > > target/riscv/helper.h | 1 + > > target/riscv/insn32.decode | 3 + > > .../riscv/insn_trans/trans_privileged.c.inc | 13 ++++ > > target/riscv/op_helper.c | 31 ++++++++++ > > 9 files changed, 224 insertions(+), 5 deletions(-) > > > > -- > > 2.17.1 > > > > >
From: Frank Chang <frank.chang@sifive.com> This patchset add suport of Resumable NMI (RNMI) in RISC-V. There are four new CSRs and one new instruction added to allow NMI to be resumable in RISC-V, which are: ============================================================= * mnscratch (0x350) * mnepc (0x351) * mncause (0x352) * mnstatus (0x353) ============================================================= * mnret: To return from RNMI interrupt/exception handler. ============================================================= RNMI also has higher priority than any other interrupts or exceptions and cannot be disable by software. RNMI may be used to route to other devices such as Bus Error Unit or Watchdog Timer in the future. The interrupt/exception trap handler addresses of RNMI are implementation defined. The technical proposal of RNMI can be found: https://lists.riscv.org/g/tech-privileged/message/421 The port is available here: https://github.com/sifive/qemu/tree/nmi-upstream-v1 To enable RNMI feature, add cpu argument: 'rnmi=true' and specify RNMI interrupt/exception handler addresses with 'rnmi_irqvec' and 'rnmi_excpvec' arguments, e.g. -cpu rv64,rnmi=true,rnmi_irqvec=0x2000,rnmi_excpvec=0x3000 Frank Chang (1): target/riscv: add support of RNMI target/riscv/cpu.c | 40 +++++++++++++ target/riscv/cpu.h | 16 ++++- target/riscv/cpu_bits.h | 19 ++++++ target/riscv/cpu_helper.c | 47 +++++++++++++-- target/riscv/csr.c | 59 +++++++++++++++++++ target/riscv/helper.h | 1 + target/riscv/insn32.decode | 3 + .../riscv/insn_trans/trans_privileged.c.inc | 13 ++++ target/riscv/op_helper.c | 31 ++++++++++ 9 files changed, 224 insertions(+), 5 deletions(-) -- 2.17.1