| Message ID | 20200623215920.2594-1-zhiwei_liu@c-sky.com |
|---|---|
| Headers | show |
| Series | target/riscv: support vector extension v0.7.1 | expand |
Patchew URL: https://patchew.org/QEMU/20200623215920.2594-1-zhiwei_liu@c-sky.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v11 00/61] target/riscv: support vector extension v0.7.1
Type: series
Message-id: 20200623215920.2594-1-zhiwei_liu@c-sky.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/1592954616-65393-1-git-send-email-fnu.vikram@xilinx.com -> patchew/1592954616-65393-1-git-send-email-fnu.vikram@xilinx.com
* [new tag] patchew/20200623215920.2594-1-zhiwei_liu@c-sky.com -> patchew/20200623215920.2594-1-zhiwei_liu@c-sky.com
Switched to a new branch 'test'
b3235da target/riscv: configure and turn on vector extension from command line
4719f6a target/riscv: vector compress instruction
1c33a5a target/riscv: vector register gather instruction
0f65e71 target/riscv: vector slide instructions
62c1869 target/riscv: floating-point scalar move instructions
73864e7 target/riscv: integer scalar move instruction
5a9e72b target/riscv: integer extract instruction
40087e9 target/riscv: vector element index instruction
aa202b8 target/riscv: vector iota instruction
8b2fb92 target/riscv: set-X-first mask bit
317ce79 target/riscv: vmfirst find-first-set mask bit
f278f6c target/riscv: vector mask population count vmpopc
5f9d471 target/riscv: vector mask-register logical instructions
6a07c65 target/riscv: vector widening floating-point reduction instructions
4d70f1f target/riscv: vector single-width floating-point reduction instructions
a7bd38a target/riscv: vector wideing integer reduction instructions
494df90 target/riscv: vector single-width integer reduction instructions
36ae952 target/riscv: narrowing floating-point/integer type-convert instructions
1e06cf3 target/riscv: widening floating-point/integer type-convert instructions
a43447b target/riscv: vector floating-point/integer type-convert instructions
7af58c7 target/riscv: vector floating-point merge instructions
ed8fdcd target/riscv: vector floating-point classify instructions
f5583ec target/riscv: vector floating-point compare instructions
a1de923 target/riscv: vector floating-point sign-injection instructions
49b2c89 target/riscv: vector floating-point min/max instructions
fa3ebf8 target/riscv: vector floating-point square-root instruction
e6ebb78 target/riscv: vector widening floating-point fused multiply-add instructions
24517f0 target/riscv: vector single-width floating-point fused multiply-add instructions
290e399 target/riscv: vector widening floating-point multiply
e2c78e8 target/riscv: vector single-width floating-point multiply/divide instructions
919de06 target/riscv: vector widening floating-point add/subtract instructions
0d86838 target/riscv: vector single-width floating-point add/subtract instructions
1513938 target/riscv: vector narrowing fixed-point clip instructions
644de02 target/riscv: vector single-width scaling shift instructions
61426f1 target/riscv: vector widening saturating scaled multiply-add
4a8b31e target/riscv: vector single-width fractional multiply with rounding and saturation
4d0ed0d target/riscv: vector single-width averaging add and subtract
5a736ec target/riscv: vector single-width saturating add and subtract
f01feef target/riscv: vector integer merge and move instructions
6a5ab25 target/riscv: vector widening integer multiply-add instructions
f2679b0 target/riscv: vector single-width integer multiply-add instructions
8885d48 target/riscv: vector widening integer multiply instructions
8bd3799 target/riscv: vector integer divide instructions
04cab04 target/riscv: vector single-width integer multiply instructions
c5e9954 target/riscv: vector integer min/max instructions
7eda907 target/riscv: vector integer comparison instructions
b7f952f target/riscv: vector narrowing integer right shift instructions
c6e20c0 target/riscv: vector single-width bit shift instructions
3c31fc6 target/riscv: vector bitwise logical instructions
3df47cb target/riscv: vector integer add-with-carry / subtract-with-borrow instructions
bae5d6b target/riscv: vector widening integer add and subtract
38f5c40 target/riscv: vector single-width integer add and subtract
fd5f85c target/riscv: add vector amo operations
afada7d target/riscv: add fault-only-first unit stride load
33e826a target/riscv: add vector index load and store instructions
ea843d3 target/riscv: add vector stride load and store instructions
843ac0f target/riscv: add an internals.h header
2481059 target/riscv: add vector configure instruction
7cc57b6 target/riscv: support vector extension csr
b394046 target/riscv: implementation-defined constant parameters
f1f9cc0 target/riscv: add vector extension field in CPURISCVState
=== OUTPUT BEGIN ===
1/61 Checking commit f1f9cc073807 (target/riscv: add vector extension field in CPURISCVState)
2/61 Checking commit b3940468b4da (target/riscv: implementation-defined constant parameters)
3/61 Checking commit 7cc57b6a5359 (target/riscv: support vector extension csr)
4/61 Checking commit 2481059eabd2 (target/riscv: add vector configure instruction)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#161:
new file mode 100644
total: 0 errors, 1 warnings, 295 lines checked
Patch 4/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/61 Checking commit 843ac0f2ac4e (target/riscv: add an internals.h header)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#16:
new file mode 100644
total: 0 errors, 1 warnings, 24 lines checked
Patch 5/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/61 Checking commit ea843d391431 (target/riscv: add vector stride load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#274: FILE: target/riscv/insn_trans/trans_rvv.inc.c:143:
+static bool trans_##NAME(DisasContext *s, arg_##ARGTYPE *a)\
^
ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+ vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#835: FILE: target/riscv/vector_helper.c:260:
+ vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+ vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#937: FILE: target/riscv/vector_helper.c:362:
+ vext_ldst_elem_fn *ldst_elem, clear_fn *clear_elem,
^
total: 5 errors, 0 warnings, 982 lines checked
Patch 6/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
7/61 Checking commit 33e826a24edf (target/riscv: add vector index load and store instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#251: FILE: target/riscv/vector_helper.c:487:
+ vext_ldst_elem_fn *ldst_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#252: FILE: target/riscv/vector_helper.c:488:
+ clear_fn *clear_elem,
^
total: 2 errors, 0 warnings, 308 lines checked
Patch 7/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
8/61 Checking commit afada7d6943e (target/riscv: add fault-only-first unit stride load)
ERROR: spaces required around that '*' (ctx:WxV)
#161: FILE: target/riscv/vector_helper.c:587:
+ vext_ldst_elem_fn *ldst_elem,
^
ERROR: spaces required around that '*' (ctx:WxV)
#162: FILE: target/riscv/vector_helper.c:588:
+ clear_fn *clear_elem,
^
total: 2 errors, 0 warnings, 227 lines checked
Patch 8/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/61 Checking commit fd5f85c3716c (target/riscv: add vector amo operations)
ERROR: spaces required around that '*' (ctx:WxV)
#365: FILE: target/riscv/vector_helper.c:770:
+ vext_amo_noatomic_fn *noatomic_op,
^
ERROR: spaces required around that '*' (ctx:WxV)
#366: FILE: target/riscv/vector_helper.c:771:
+ clear_fn *clear_elem,
^
total: 2 errors, 0 warnings, 382 lines checked
Patch 9/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/61 Checking commit 38f5c405398c (target/riscv: vector single-width integer add and subtract)
ERROR: spaces required around that '*' (ctx:WxV)
#93: FILE: target/riscv/insn_trans/trans_rvv.inc.c:781:
+static bool opivv_check(DisasContext *s, arg_rmrr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:876:
+ opivv2_fn *fn, clear_fn *clearfn)
^
ERROR: spaces required around that '*' (ctx:WxV)
#425: FILE: target/riscv/vector_helper.c:876:
+ opivv2_fn *fn, clear_fn *clearfn)
^
ERROR: spaces required around that '*' (ctx:WxV)
#490: FILE: target/riscv/vector_helper.c:941:
+ opivx2_fn fn, clear_fn *clearfn)
^
total: 4 errors, 0 warnings, 535 lines checked
Patch 10/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/61 Checking commit bae5d6b8acf5 (target/riscv: vector widening integer add and subtract)
12/61 Checking commit 3df47cb13916 (target/riscv: vector integer add-with-carry / subtract-with-borrow instructions)
13/61 Checking commit 3c31fc6657d1 (target/riscv: vector bitwise logical instructions)
14/61 Checking commit c6e20c0746ba (target/riscv: vector single-width bit shift instructions)
15/61 Checking commit b7f952ffe66c (target/riscv: vector narrowing integer right shift instructions)
16/61 Checking commit 7eda907ddae3 (target/riscv: vector integer comparison instructions)
17/61 Checking commit c5e99549e341 (target/riscv: vector integer min/max instructions)
18/61 Checking commit 04cab0415a7d (target/riscv: vector single-width integer multiply instructions)
19/61 Checking commit 8bd3799c49df (target/riscv: vector integer divide instructions)
20/61 Checking commit 8885d482863c (target/riscv: vector widening integer multiply instructions)
21/61 Checking commit f2679b048d86 (target/riscv: vector single-width integer multiply-add instructions)
22/61 Checking commit 6a5ab2501411 (target/riscv: vector widening integer multiply-add instructions)
23/61 Checking commit f01feefe8723 (target/riscv: vector integer merge and move instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#72: FILE: target/riscv/insn_trans/trans_rvv.inc.c:1623:
+static bool trans_vmv_v_v(DisasContext *s, arg_vmv_v_v *a)
^
total: 1 errors, 0 warnings, 246 lines checked
Patch 23/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
24/61 Checking commit 5a736ec91e35 (target/riscv: vector single-width saturating add and subtract)
25/61 Checking commit 4d0ed0d9dbca (target/riscv: vector single-width averaging add and subtract)
26/61 Checking commit 4a8b31ed0eae (target/riscv: vector single-width fractional multiply with rounding and saturation)
27/61 Checking commit 61426f145e48 (target/riscv: vector widening saturating scaled multiply-add)
28/61 Checking commit 644de02fefb2 (target/riscv: vector single-width scaling shift instructions)
29/61 Checking commit 1513938abce3 (target/riscv: vector narrowing fixed-point clip instructions)
30/61 Checking commit 0d86838ad955 (target/riscv: vector single-width floating-point add/subtract instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#283: FILE: target/riscv/vector_helper.c:3260:
+static uint16_t float16_rsub(uint16_t a, uint16_t b, float_status *s)
^
total: 1 errors, 0 warnings, 271 lines checked
Patch 30/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
31/61 Checking commit 919de066251f (target/riscv: vector widening floating-point add/subtract instructions)
32/61 Checking commit e2c78e8f5c17 (target/riscv: vector single-width floating-point multiply/divide instructions)
33/61 Checking commit 290e3991bed3 (target/riscv: vector widening floating-point multiply)
34/61 Checking commit 24517f05f994 (target/riscv: vector single-width floating-point fused multiply-add instructions)
35/61 Checking commit e6ebb7813f14 (target/riscv: vector widening floating-point fused multiply-add instructions)
36/61 Checking commit fa3ebf8a0085 (target/riscv: vector floating-point square-root instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#67: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2099:
+static bool opfv_check(DisasContext *s, arg_rmr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#77: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2109:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
^
total: 2 errors, 0 warnings, 120 lines checked
Patch 36/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
37/61 Checking commit 49b2c8955e28 (target/riscv: vector floating-point min/max instructions)
38/61 Checking commit a1de923f6d62 (target/riscv: vector floating-point sign-injection instructions)
39/61 Checking commit f5583ec30f39 (target/riscv: vector floating-point compare instructions)
40/61 Checking commit ed8fdcd013f5 (target/riscv: vector floating-point classify instructions)
41/61 Checking commit 7af58c7d39d5 (target/riscv: vector floating-point merge instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#49: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2191:
+static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
^
total: 1 errors, 0 warnings, 83 lines checked
Patch 41/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
42/61 Checking commit a43447b51251 (target/riscv: vector floating-point/integer type-convert instructions)
43/61 Checking commit 1e06cf3d965b (target/riscv: widening floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2238:
+static bool opfv_widen_check(DisasContext *s, arg_rmr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2250:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
^
total: 2 errors, 0 warnings, 121 lines checked
Patch 43/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
44/61 Checking commit 36ae95295971 (target/riscv: narrowing floating-point/integer type-convert instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2286:
+static bool opfv_narrow_check(DisasContext *s, arg_rmr *a)
^
ERROR: spaces required around that '*' (ctx:WxV)
#74: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2298:
+static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
^
total: 2 errors, 0 warnings, 118 lines checked
Patch 44/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
45/61 Checking commit 494df90c1b08 (target/riscv: vector single-width integer reduction instructions)
46/61 Checking commit a7bd38a4943a (target/riscv: vector wideing integer reduction instructions)
47/61 Checking commit 4d70f1fa87d3 (target/riscv: vector single-width floating-point reduction instructions)
48/61 Checking commit 6a07c6539905 (target/riscv: vector widening floating-point reduction instructions)
49/61 Checking commit 5f9d471a77cf (target/riscv: vector mask-register logical instructions)
ERROR: spaces required around that '*' (ctx:WxV)
#62: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2364:
+static bool trans_##NAME(DisasContext *s, arg_r *a) \
^
total: 1 errors, 0 warnings, 107 lines checked
Patch 49/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
50/61 Checking commit f278f6cb84fa (target/riscv: vector mask population count vmpopc)
ERROR: spaces required around that '*' (ctx:WxV)
#43: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2394:
+static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
^
total: 1 errors, 0 warnings, 70 lines checked
Patch 50/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
51/61 Checking commit 317ce7999243 (target/riscv: vmfirst find-first-set mask bit)
52/61 Checking commit 8b2fb9243545 (target/riscv: set-X-first mask bit)
53/61 Checking commit aa202b82ff10 (target/riscv: vector iota instruction)
ERROR: spaces required around that '*' (ctx:WxV)
#46: FILE: target/riscv/insn_trans/trans_rvv.inc.c:2486:
+static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
^
total: 1 errors, 0 warnings, 77 lines checked
Patch 53/61 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
54/61 Checking commit 40087e98e34e (target/riscv: vector element index instruction)
55/61 Checking commit 5a9e72b8d72b (target/riscv: integer extract instruction)
56/61 Checking commit 73864e708050 (target/riscv: integer scalar move instruction)
57/61 Checking commit 62c1869a2a65 (target/riscv: floating-point scalar move instructions)
58/61 Checking commit 0f65e719fd35 (target/riscv: vector slide instructions)
59/61 Checking commit 1c33a5ac127c (target/riscv: vector register gather instruction)
60/61 Checking commit 4719f6a2a943 (target/riscv: vector compress instruction)
61/61 Checking commit b3235da17cf7 (target/riscv: configure and turn on vector extension from command line)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20200623215920.2594-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
On Tue, Jun 23, 2020 at 3:00 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > This patchset implements the vector extension for RISC-V on QEMU. > > You can also find the patchset and all *test cases* in > my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v11). > All the test cases are in the directory qemu/tests/riscv/vector/. They are > riscv64 linux user mode programs. > > You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh. > > Features: > * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/) > * support basic vector extension. > * support Zvlsseg. > * support Zvamo. > * not support Zvediv as it is changing. > * SLEN always equals VLEN. > * element width support 8bit, 16bit, 32bit, 64bit. > > Changelog: > > v11 > * fix all non-ASCII characters. > > v10 > * rebase to https://github.com/alistair23/qemu/tree/riscv-to-apply.next. > * fix compile error in patch 57/61. > * fix review tag typo. > > v9 > * always set dynamic rounding mode for vector float insns. > * bug fix atomic implementation. > * bug fix first-only-fault. > * some small tidy up. > > v8 > * support different float rounding modes for vector instructions. > * use lastest released TCG GVEC DUP IR. > * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc. > > v7 > * move vl == 0 check to translation time by add a global cpu_vl. > * implement vector element inline load and store function by TCG IR. > * based on vec_element_load(store), implement some permutation instructions. > * implement rsubs GVEC IR. > * fixup vsmul, vmfne, vfmerge, vslidedown. > * some other small bugs and indentation errors. > > v6 > * use gvec_dup Gvec IR to accellerate move and merge. > * a better way to implement fixed point instructions. > * a global check when vl == 0. > * limit some macros to only one inline function call. > * fixup sew error when use Gvec IR. > * fixup bugs for corner cases. > > v5 > * fixup a bug in tb flags. > > v4 > * no change > > v3 > * move check code from execution-time to translation-time > * use a continous memory block for vector register description. > * vector registers as direct fields in RISCVCPUState. > * support VLEN configure from qemu command line. > * support ELEN configure from qemu command line. > * support vector specification version configure from qemu command line. > * probe pages before real load or store access. > * use probe_page_check for no-fault operations in linux user mode. > * generation atomic exit exception when in parallel environment. > * fixup a lot of concrete bugs. > > V2 > * use float16_compare{_quiet} > * only use GETPC() in outer most helper > * add ctx.ext_v Property > > > > LIU Zhiwei (61): > target/riscv: add vector extension field in CPURISCVState > target/riscv: implementation-defined constant parameters > target/riscv: support vector extension csr > target/riscv: add vector configure instruction > target/riscv: add an internals.h header > target/riscv: add vector stride load and store instructions > target/riscv: add vector index load and store instructions > target/riscv: add fault-only-first unit stride load > target/riscv: add vector amo operations > target/riscv: vector single-width integer add and subtract > target/riscv: vector widening integer add and subtract > target/riscv: vector integer add-with-carry / subtract-with-borrow > instructions > target/riscv: vector bitwise logical instructions > target/riscv: vector single-width bit shift instructions > target/riscv: vector narrowing integer right shift instructions > target/riscv: vector integer comparison instructions > target/riscv: vector integer min/max instructions > target/riscv: vector single-width integer multiply instructions > target/riscv: vector integer divide instructions > target/riscv: vector widening integer multiply instructions > target/riscv: vector single-width integer multiply-add instructions > target/riscv: vector widening integer multiply-add instructions > target/riscv: vector integer merge and move instructions > target/riscv: vector single-width saturating add and subtract > target/riscv: vector single-width averaging add and subtract > target/riscv: vector single-width fractional multiply with rounding > and saturation > target/riscv: vector widening saturating scaled multiply-add > target/riscv: vector single-width scaling shift instructions > target/riscv: vector narrowing fixed-point clip instructions > target/riscv: vector single-width floating-point add/subtract > instructions > target/riscv: vector widening floating-point add/subtract instructions > target/riscv: vector single-width floating-point multiply/divide > instructions > target/riscv: vector widening floating-point multiply > target/riscv: vector single-width floating-point fused multiply-add > instructions > target/riscv: vector widening floating-point fused multiply-add > instructions > target/riscv: vector floating-point square-root instruction > target/riscv: vector floating-point min/max instructions > target/riscv: vector floating-point sign-injection instructions > target/riscv: vector floating-point compare instructions > target/riscv: vector floating-point classify instructions > target/riscv: vector floating-point merge instructions > target/riscv: vector floating-point/integer type-convert instructions > target/riscv: widening floating-point/integer type-convert > instructions > target/riscv: narrowing floating-point/integer type-convert > instructions > target/riscv: vector single-width integer reduction instructions > target/riscv: vector wideing integer reduction instructions > target/riscv: vector single-width floating-point reduction > instructions > target/riscv: vector widening floating-point reduction instructions > target/riscv: vector mask-register logical instructions > target/riscv: vector mask population count vmpopc > target/riscv: vmfirst find-first-set mask bit > target/riscv: set-X-first mask bit > target/riscv: vector iota instruction > target/riscv: vector element index instruction > target/riscv: integer extract instruction > target/riscv: integer scalar move instruction > target/riscv: floating-point scalar move instructions > target/riscv: vector slide instructions > target/riscv: vector register gather instruction > target/riscv: vector compress instruction > target/riscv: configure and turn on vector extension from command line Thanks! Applied to the RISC-V tree. Alistair > > target/riscv/Makefile.objs | 2 +- > target/riscv/cpu.c | 50 + > target/riscv/cpu.h | 82 +- > target/riscv/cpu_bits.h | 15 + > target/riscv/csr.c | 75 +- > target/riscv/fpu_helper.c | 33 +- > target/riscv/helper.h | 1069 +++++ > target/riscv/insn32-64.decode | 11 + > target/riscv/insn32.decode | 372 ++ > target/riscv/insn_trans/trans_rvv.inc.c | 2888 +++++++++++++ > target/riscv/internals.h | 41 + > target/riscv/translate.c | 27 +- > target/riscv/vector_helper.c | 4899 +++++++++++++++++++++++ > 13 files changed, 9520 insertions(+), 44 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c > create mode 100644 target/riscv/internals.h > create mode 100644 target/riscv/vector_helper.c > > -- > 2.23.0 > >
This patchset implements the vector extension for RISC-V on QEMU. You can also find the patchset and all *test cases* in my repo(https://github.com/romanheros/qemu.git branch:vector-upstream-v11). All the test cases are in the directory qemu/tests/riscv/vector/. They are riscv64 linux user mode programs. You can test the patchset by the script qemu/tests/riscv/vector/runcase.sh. Features: * support specification riscv-v-spec-0.7.1.(https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1/) * support basic vector extension. * support Zvlsseg. * support Zvamo. * not support Zvediv as it is changing. * SLEN always equals VLEN. * element width support 8bit, 16bit, 32bit, 64bit. Changelog: v11 * fix all non-ASCII characters. v10 * rebase to https://github.com/alistair23/qemu/tree/riscv-to-apply.next. * fix compile error in patch 57/61. * fix review tag typo. v9 * always set dynamic rounding mode for vector float insns. * bug fix atomic implementation. * bug fix first-only-fault. * some small tidy up. v8 * support different float rounding modes for vector instructions. * use lastest released TCG GVEC DUP IR. * set RV_VLEN_MAX to 256 bits, as GVEC IR uses simd_desc. v7 * move vl == 0 check to translation time by add a global cpu_vl. * implement vector element inline load and store function by TCG IR. * based on vec_element_load(store), implement some permutation instructions. * implement rsubs GVEC IR. * fixup vsmul, vmfne, vfmerge, vslidedown. * some other small bugs and indentation errors. v6 * use gvec_dup Gvec IR to accellerate move and merge. * a better way to implement fixed point instructions. * a global check when vl == 0. * limit some macros to only one inline function call. * fixup sew error when use Gvec IR. * fixup bugs for corner cases. v5 * fixup a bug in tb flags. v4 * no change v3 * move check code from execution-time to translation-time * use a continous memory block for vector register description. * vector registers as direct fields in RISCVCPUState. * support VLEN configure from qemu command line. * support ELEN configure from qemu command line. * support vector specification version configure from qemu command line. * probe pages before real load or store access. * use probe_page_check for no-fault operations in linux user mode. * generation atomic exit exception when in parallel environment. * fixup a lot of concrete bugs. V2 * use float16_compare{_quiet} * only use GETPC() in outer most helper * add ctx.ext_v Property LIU Zhiwei (61): target/riscv: add vector extension field in CPURISCVState target/riscv: implementation-defined constant parameters target/riscv: support vector extension csr target/riscv: add vector configure instruction target/riscv: add an internals.h header target/riscv: add vector stride load and store instructions target/riscv: add vector index load and store instructions target/riscv: add fault-only-first unit stride load target/riscv: add vector amo operations target/riscv: vector single-width integer add and subtract target/riscv: vector widening integer add and subtract target/riscv: vector integer add-with-carry / subtract-with-borrow instructions target/riscv: vector bitwise logical instructions target/riscv: vector single-width bit shift instructions target/riscv: vector narrowing integer right shift instructions target/riscv: vector integer comparison instructions target/riscv: vector integer min/max instructions target/riscv: vector single-width integer multiply instructions target/riscv: vector integer divide instructions target/riscv: vector widening integer multiply instructions target/riscv: vector single-width integer multiply-add instructions target/riscv: vector widening integer multiply-add instructions target/riscv: vector integer merge and move instructions target/riscv: vector single-width saturating add and subtract target/riscv: vector single-width averaging add and subtract target/riscv: vector single-width fractional multiply with rounding and saturation target/riscv: vector widening saturating scaled multiply-add target/riscv: vector single-width scaling shift instructions target/riscv: vector narrowing fixed-point clip instructions target/riscv: vector single-width floating-point add/subtract instructions target/riscv: vector widening floating-point add/subtract instructions target/riscv: vector single-width floating-point multiply/divide instructions target/riscv: vector widening floating-point multiply target/riscv: vector single-width floating-point fused multiply-add instructions target/riscv: vector widening floating-point fused multiply-add instructions target/riscv: vector floating-point square-root instruction target/riscv: vector floating-point min/max instructions target/riscv: vector floating-point sign-injection instructions target/riscv: vector floating-point compare instructions target/riscv: vector floating-point classify instructions target/riscv: vector floating-point merge instructions target/riscv: vector floating-point/integer type-convert instructions target/riscv: widening floating-point/integer type-convert instructions target/riscv: narrowing floating-point/integer type-convert instructions target/riscv: vector single-width integer reduction instructions target/riscv: vector wideing integer reduction instructions target/riscv: vector single-width floating-point reduction instructions target/riscv: vector widening floating-point reduction instructions target/riscv: vector mask-register logical instructions target/riscv: vector mask population count vmpopc target/riscv: vmfirst find-first-set mask bit target/riscv: set-X-first mask bit target/riscv: vector iota instruction target/riscv: vector element index instruction target/riscv: integer extract instruction target/riscv: integer scalar move instruction target/riscv: floating-point scalar move instructions target/riscv: vector slide instructions target/riscv: vector register gather instruction target/riscv: vector compress instruction target/riscv: configure and turn on vector extension from command line target/riscv/Makefile.objs | 2 +- target/riscv/cpu.c | 50 + target/riscv/cpu.h | 82 +- target/riscv/cpu_bits.h | 15 + target/riscv/csr.c | 75 +- target/riscv/fpu_helper.c | 33 +- target/riscv/helper.h | 1069 +++++ target/riscv/insn32-64.decode | 11 + target/riscv/insn32.decode | 372 ++ target/riscv/insn_trans/trans_rvv.inc.c | 2888 +++++++++++++ target/riscv/internals.h | 41 + target/riscv/translate.c | 27 +- target/riscv/vector_helper.c | 4899 +++++++++++++++++++++++ 13 files changed, 9520 insertions(+), 44 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvv.inc.c create mode 100644 target/riscv/internals.h create mode 100644 target/riscv/vector_helper.c