| Message ID | 20200130112510.15154-1-eric.auger@redhat.com |
|---|---|
| Headers | show |
| Series | KVM: arm64: PMUv3 Event Counter Tests | expand |
On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: > > This series implements tests exercising the PMUv3 event counters. > It tests both the 32-bit and 64-bit versions. Overflow interrupts > also are checked. Those tests only are written for arm64. > > It allowed to reveal some issues related to SW_INCR implementation > (esp. related to 64-bit implementation), some problems related to > 32-bit <-> 64-bit transitions and consistency of enabled states > of odd and event counters (See [1]). > > Overflow interrupt testing relies of one patch from Andre > ("arm: gic: Provide per-IRQ helper functions") to enable the > PPI 23, coming from "arm: gic: Test SPIs and interrupt groups" > (https://patchwork.kernel.org/cover/11234975/). Drew kindly > provided "arm64: Provide read/write_sysreg_s". > > All PMU tests can be launched with: > ./run_tests.sh -g pmu > Tests also can be launched individually. For example: > ./arm-run arm/pmu.flat -append 'chained-sw-incr' > > With KVM: > - chain-promotion and chained-sw-incr are known to be failing. > [1] proposed a fix. > - On TX2, I have some random failures due to MEM_ACCESS event > measured with a great disparity. This is not observed on > other machines I have access to. > With TCG: > - all new tests are skipped I'm having a go at using this patchset to test the support I'm adding for TCG for the v8.1 and v8.4 PMU extensions... Q1: how can I get run_tests.sh to pass extra arguments to QEMU ? The PMU events check will fail unless QEMU gets the '-icount 8' to enable cycle-counting, but although the underlying ./arm/run lets you add arbitrary extra arguments to QEMU, run_tests.sh doesn't seem to. Trying to pass them in via "QEMU=/path/to/qemu -icount 8" doesn't work either. Q2: do you know why arm/pmu.c:check_pmcr() insists that PMCR.IMP is non-zero? The comment says "simple sanity check", but architecturally a zero IMP field is permitted (meaning "go look at MIDR_EL1 instead"). This causes TCG to fail this test on '-cpu max', because in that case we set PMCR.IMP to the same thing as MIDR_EL1.Implementer which is 0 ("software use", since QEMU is software...) thanks -- PMM
On Tue, Feb 11, 2020 at 03:42:38PM +0000, Peter Maydell wrote: > On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: > > > > This series implements tests exercising the PMUv3 event counters. > > It tests both the 32-bit and 64-bit versions. Overflow interrupts > > also are checked. Those tests only are written for arm64. > > > > It allowed to reveal some issues related to SW_INCR implementation > > (esp. related to 64-bit implementation), some problems related to > > 32-bit <-> 64-bit transitions and consistency of enabled states > > of odd and event counters (See [1]). > > > > Overflow interrupt testing relies of one patch from Andre > > ("arm: gic: Provide per-IRQ helper functions") to enable the > > PPI 23, coming from "arm: gic: Test SPIs and interrupt groups" > > (https://patchwork.kernel.org/cover/11234975/). Drew kindly > > provided "arm64: Provide read/write_sysreg_s". > > > > All PMU tests can be launched with: > > ./run_tests.sh -g pmu > > Tests also can be launched individually. For example: > > ./arm-run arm/pmu.flat -append 'chained-sw-incr' > > > > With KVM: > > - chain-promotion and chained-sw-incr are known to be failing. > > [1] proposed a fix. > > - On TX2, I have some random failures due to MEM_ACCESS event > > measured with a great disparity. This is not observed on > > other machines I have access to. > > With TCG: > > - all new tests are skipped > > I'm having a go at using this patchset to test the support > I'm adding for TCG for the v8.1 and v8.4 PMU extensions... > > Q1: how can I get run_tests.sh to pass extra arguments to > QEMU ? The PMU events check will fail unless QEMU gets > the '-icount 8' to enable cycle-counting, but although > the underlying ./arm/run lets you add arbitrary extra > arguments to QEMU, run_tests.sh doesn't seem to. Trying to > pass them in via "QEMU=/path/to/qemu -icount 8" doesn't > work either. Alex Bennee once submit a patch[*] allowing that to work, but it never got merged. I just rebased it and tried it, but it doesn't work now. Too much has changed in the run scripts since his posting. I can try to rework it though. [*] https://github.com/rhdrjones/kvm-unit-tests/commit/9a8574bfd924f3e865611688e26bb12e53821747 > > Q2: do you know why arm/pmu.c:check_pmcr() insists that > PMCR.IMP is non-zero? The comment says "simple sanity check", > but architecturally a zero IMP field is permitted (meaning > "go look at MIDR_EL1 instead"). This causes TCG to fail this > test on '-cpu max', because in that case we set PMCR.IMP > to the same thing as MIDR_EL1.Implementer which is 0 > ("software use", since QEMU is software...) Probably just a misunderstanding on the part of the author (and reviewers). Maybe Eric can fix that while preparing this series. Thanks, drew
On 2/11/20 5:07 PM, Andrew Jones wrote: > On Tue, Feb 11, 2020 at 03:42:38PM +0000, Peter Maydell wrote: >> On Thu, 30 Jan 2020 at 11:25, Eric Auger <eric.auger@redhat.com> wrote: >>> >>> This series implements tests exercising the PMUv3 event counters. >>> It tests both the 32-bit and 64-bit versions. Overflow interrupts >>> also are checked. Those tests only are written for arm64. >>> >>> It allowed to reveal some issues related to SW_INCR implementation >>> (esp. related to 64-bit implementation), some problems related to >>> 32-bit <-> 64-bit transitions and consistency of enabled states >>> of odd and event counters (See [1]). >>> >>> Overflow interrupt testing relies of one patch from Andre >>> ("arm: gic: Provide per-IRQ helper functions") to enable the >>> PPI 23, coming from "arm: gic: Test SPIs and interrupt groups" >>> (https://patchwork.kernel.org/cover/11234975/). Drew kindly >>> provided "arm64: Provide read/write_sysreg_s". >>> >>> All PMU tests can be launched with: >>> ./run_tests.sh -g pmu >>> Tests also can be launched individually. For example: >>> ./arm-run arm/pmu.flat -append 'chained-sw-incr' >>> >>> With KVM: >>> - chain-promotion and chained-sw-incr are known to be failing. >>> [1] proposed a fix. >>> - On TX2, I have some random failures due to MEM_ACCESS event >>> measured with a great disparity. This is not observed on >>> other machines I have access to. >>> With TCG: >>> - all new tests are skipped >> >> I'm having a go at using this patchset to test the support >> I'm adding for TCG for the v8.1 and v8.4 PMU extensions... >> >> Q1: how can I get run_tests.sh to pass extra arguments to >> QEMU ? The PMU events check will fail unless QEMU gets >> the '-icount 8' to enable cycle-counting, but although >> the underlying ./arm/run lets you add arbitrary extra >> arguments to QEMU, run_tests.sh doesn't seem to. Trying to >> pass them in via "QEMU=/path/to/qemu -icount 8" doesn't >> work either. int arm/unittests.cfg there are tests related to TCG that are commented. # Test PMU support (TCG) with -icount IPC=256 #[pmu-tcg-icount-256] #file = pmu.flat #extra_params = -icount 8 -append 'cycle-counter 256' #groups = pmu #accel = tcg I wondered why we kept those and commented. Should we start with separate tests for KVM and TCG? > > Alex Bennee once submit a patch[*] allowing that to work, but > it never got merged. I just rebased it and tried it, but it > doesn't work now. Too much has changed in the run scripts > since his posting. I can try to rework it though. > > [*] https://github.com/rhdrjones/kvm-unit-tests/commit/9a8574bfd924f3e865611688e26bb12e53821747 > >> >> Q2: do you know why arm/pmu.c:check_pmcr() insists that >> PMCR.IMP is non-zero? The comment says "simple sanity check", >> but architecturally a zero IMP field is permitted (meaning >> "go look at MIDR_EL1 instead"). This causes TCG to fail this >> test on '-cpu max', because in that case we set PMCR.IMP >> to the same thing as MIDR_EL1.Implementer which is 0 >> ("software use", since QEMU is software...) indeed > > Probably just a misunderstanding on the part of the author (and > reviewers). Maybe Eric can fix that while preparing this series. Yes I can definitively fix that Thanks Eric > > Thanks, > drew >
This series implements tests exercising the PMUv3 event counters. It tests both the 32-bit and 64-bit versions. Overflow interrupts also are checked. Those tests only are written for arm64. It allowed to reveal some issues related to SW_INCR implementation (esp. related to 64-bit implementation), some problems related to 32-bit <-> 64-bit transitions and consistency of enabled states of odd and event counters (See [1]). Overflow interrupt testing relies of one patch from Andre ("arm: gic: Provide per-IRQ helper functions") to enable the PPI 23, coming from "arm: gic: Test SPIs and interrupt groups" (https://patchwork.kernel.org/cover/11234975/). Drew kindly provided "arm64: Provide read/write_sysreg_s". All PMU tests can be launched with: ./run_tests.sh -g pmu Tests also can be launched individually. For example: ./arm-run arm/pmu.flat -append 'chained-sw-incr' With KVM: - chain-promotion and chained-sw-incr are known to be failing. [1] proposed a fix. - On TX2, I have some random failures due to MEM_ACCESS event measured with a great disparity. This is not observed on other machines I have access to. With TCG: - all new tests are skipped The series can be found at: https://github.com/eauger/kut/tree/pmu_event_counters_v2 References: [1] [PATCH 0/4] KVM/ARM: Misc PMU fixes (https://www.spinics.net/lists/kvm-arm/msg38886.html) History: - Took into account Andre's comments except I did not use cnbz in the mem_access_loop() and I did not use @loop directly. Those changes had side effects I cannot explain on the tests. Anyway I think this can be improved later on. - removed [kvm-unit-tests PATCH 09/10] arm/arm64: gic: Introduce setup_irq() helper RFC -> v1: - Use new report() proto - Style cleanup - do not warn about ARM spec recommendations - add a comment about PMCEID0/1 splits Andre Przywara (1): arm: gic: Provide per-IRQ helper functions Andrew Jones (1): arm64: Provide read/write_sysreg_s Eric Auger (7): arm: pmu: Let pmu tests take a sub-test parameter arm: pmu: Add a pmu struct arm: pmu: Check Required Event Support arm: pmu: Basic event counter Tests arm: pmu: Test chained counter arm: pmu: test 32-bit <-> 64-bit transitions arm: pmu: Test overflow interrupts arm/pmu.c | 786 ++++++++++++++++++++++++++++++++++++++++- arm/unittests.cfg | 55 ++- lib/arm/asm/gic-v3.h | 2 + lib/arm/asm/gic.h | 9 + lib/arm/gic.c | 90 +++++ lib/arm64/asm/sysreg.h | 11 + 6 files changed, 936 insertions(+), 17 deletions(-)