| Message ID | 20180820153020.21478-1-peter.maydell@linaro.org |
|---|---|
| Headers | show |
| Series | target/arm: Some pieces of support for 32-bit Hyp mode | expand |
On 08/20/2018 08:30 AM, Peter Maydell wrote: > Peter Maydell (6): > target/arm: Implement RAZ/WI HACTLR2 > target/arm: Implement AArch32 HCR and HCR2 > target/arm: Factor out code for taking an AArch32 exception > target/arm: Implement support for taking exceptions to Hyp mode > target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry > hw/arm/boot: AArch32 kernels should be started in Hyp mode if > available Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Mon, Aug 20, 2018 at 04:30:14PM +0100, Peter Maydell wrote: > Now we have virtualization support in the GICv2 emulation, > I thought I'd have a look at how much we were still missing > for being able to enable EL2 support for AArch32. > This set of patches fixes some minor missing pieces: > * AArch32 HACTLR2 > * AArch32 HCR, HCR2 > * support for taking exceptions to Hyp mode > * boot AArch32 kernels in Hyp mode where available > and I threw in a trivial bugfix: > * Clear CPSR.IL and CPSR.J on 32-bit exception entry > since it would otherwise have a conflict with the refactoring > of exception entry. > > Changes v1->v2: > * some patches are now upstream > * v8-only registers no longer created for v7 CPUs > * split the "factor out exception-entry code" into > its own patch > * new patch: clear CPSR.IL and CPSR.J > * new patch: boot kernels in Hyp mode if possible > > (I still have the same "guest EL0 segv" issue as for v1 > if I actually enable the EL2 feature on Cortex-A15.) Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> > > thanks > -- PMM > > Peter Maydell (6): > target/arm: Implement RAZ/WI HACTLR2 > target/arm: Implement AArch32 HCR and HCR2 > target/arm: Factor out code for taking an AArch32 exception > target/arm: Implement support for taking exceptions to Hyp mode > target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry > hw/arm/boot: AArch32 kernels should be started in Hyp mode if > available > > hw/arm/boot.c | 11 +++ > target/arm/helper.c | 212 ++++++++++++++++++++++++++++++++++++++------ > 2 files changed, 196 insertions(+), 27 deletions(-) > > -- > 2.18.0 >
On 8/20/18 5:30 PM, Peter Maydell wrote: > Now we have virtualization support in the GICv2 emulation, > I thought I'd have a look at how much we were still missing > for being able to enable EL2 support for AArch32. > This set of patches fixes some minor missing pieces: > * AArch32 HACTLR2 > * AArch32 HCR, HCR2 > * support for taking exceptions to Hyp mode > * boot AArch32 kernels in Hyp mode where available > and I threw in a trivial bugfix: > * Clear CPSR.IL and CPSR.J on 32-bit exception entry > since it would otherwise have a conflict with the refactoring > of exception entry. > > Changes v1->v2: > * some patches are now upstream > * v8-only registers no longer created for v7 CPUs > * split the "factor out exception-entry code" into > its own patch > * new patch: clear CPSR.IL and CPSR.J > * new patch: boot kernels in Hyp mode if possible > > (I still have the same "guest EL0 segv" issue as for v1 > if I actually enable the EL2 feature on Cortex-A15.) > Reviewed-By: Luc Michel <luc.michel@greensocs.com> > thanks > -- PMM > > Peter Maydell (6): > target/arm: Implement RAZ/WI HACTLR2 > target/arm: Implement AArch32 HCR and HCR2 > target/arm: Factor out code for taking an AArch32 exception > target/arm: Implement support for taking exceptions to Hyp mode > target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry > hw/arm/boot: AArch32 kernels should be started in Hyp mode if > available > > hw/arm/boot.c | 11 +++ > target/arm/helper.c | 212 ++++++++++++++++++++++++++++++++++++++------ > 2 files changed, 196 insertions(+), 27 deletions(-) >
Now we have virtualization support in the GICv2 emulation, I thought I'd have a look at how much we were still missing for being able to enable EL2 support for AArch32. This set of patches fixes some minor missing pieces: * AArch32 HACTLR2 * AArch32 HCR, HCR2 * support for taking exceptions to Hyp mode * boot AArch32 kernels in Hyp mode where available and I threw in a trivial bugfix: * Clear CPSR.IL and CPSR.J on 32-bit exception entry since it would otherwise have a conflict with the refactoring of exception entry. Changes v1->v2: * some patches are now upstream * v8-only registers no longer created for v7 CPUs * split the "factor out exception-entry code" into its own patch * new patch: clear CPSR.IL and CPSR.J * new patch: boot kernels in Hyp mode if possible (I still have the same "guest EL0 segv" issue as for v1 if I actually enable the EL2 feature on Cortex-A15.) thanks -- PMM Peter Maydell (6): target/arm: Implement RAZ/WI HACTLR2 target/arm: Implement AArch32 HCR and HCR2 target/arm: Factor out code for taking an AArch32 exception target/arm: Implement support for taking exceptions to Hyp mode target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry hw/arm/boot: AArch32 kernels should be started in Hyp mode if available hw/arm/boot.c | 11 +++ target/arm/helper.c | 212 ++++++++++++++++++++++++++++++++++++++------ 2 files changed, 196 insertions(+), 27 deletions(-)