| Message ID | 8cbdcfc4446154bd3323cc68827f114aa9bbc5e7.1617816138.git.christophe.leroy@csgroup.eu (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1,1/8] powerpc/mem: Declare __flush_dcache_icache() static | expand |
| Related | show |
| Context | Check | Description |
|---|---|---|
| snowpatch_ozlabs/apply_patch | success | Successfully applied on branch powerpc/merge (571b0d1ccf5cd3dc1b9866a908769ee23f7d127e) |
| snowpatch_ozlabs/checkpatch | success | total: 0 errors, 0 warnings, 0 checks, 45 lines checked |
| snowpatch_ozlabs/needsstable | success | Patch has no Fixes tags |
Christophe Leroy <christophe.leroy@csgroup.eu> writes: > flush_coherent_icache() can use any valid address as mentionned > by the comment. > > Use PAGE_OFFSET as base address. This allows removing the > user access stuff. > > Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> > --- > arch/powerpc/mm/mem.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c > index ce6c81ce4362..19f807b87697 100644 > --- a/arch/powerpc/mm/mem.c > +++ b/arch/powerpc/mm/mem.c > @@ -342,10 +342,9 @@ void free_initmem(void) > > /** > * flush_coherent_icache() - if a CPU has a coherent icache, flush it > - * @addr: The base address to use (can be any valid address, the whole cache will be flushed) > * Return true if the cache was flushed, false otherwise > */ > -static inline bool flush_coherent_icache(unsigned long addr) > +static inline bool flush_coherent_icache(void) > { > /* > * For a snooping icache, we still need a dummy icbi to purge all the > @@ -355,9 +354,7 @@ static inline bool flush_coherent_icache(unsigned long addr) > */ > if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) { > mb(); /* sync */ > - allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES); > - icbi((void *)addr); > - prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES); > + icbi((void *)PAGE_OFFSET); > mb(); /* sync */ > isync(); > return true; do we need that followup sync? Usermanual suggest sync; icbi(any address); isync sequence. -aneesh
Le 08/04/2021 à 10:50, Aneesh Kumar K.V a écrit : > Christophe Leroy <christophe.leroy@csgroup.eu> writes: > >> flush_coherent_icache() can use any valid address as mentionned >> by the comment. >> >> Use PAGE_OFFSET as base address. This allows removing the >> user access stuff. >> >> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> >> --- >> arch/powerpc/mm/mem.c | 13 +++++-------- >> 1 file changed, 5 insertions(+), 8 deletions(-) >> >> diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c >> index ce6c81ce4362..19f807b87697 100644 >> --- a/arch/powerpc/mm/mem.c >> +++ b/arch/powerpc/mm/mem.c >> @@ -342,10 +342,9 @@ void free_initmem(void) >> >> /** >> * flush_coherent_icache() - if a CPU has a coherent icache, flush it >> - * @addr: The base address to use (can be any valid address, the whole cache will be flushed) >> * Return true if the cache was flushed, false otherwise >> */ >> -static inline bool flush_coherent_icache(unsigned long addr) >> +static inline bool flush_coherent_icache(void) >> { >> /* >> * For a snooping icache, we still need a dummy icbi to purge all the >> @@ -355,9 +354,7 @@ static inline bool flush_coherent_icache(unsigned long addr) >> */ >> if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) { >> mb(); /* sync */ >> - allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES); >> - icbi((void *)addr); >> - prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES); >> + icbi((void *)PAGE_OFFSET); >> mb(); /* sync */ >> isync(); >> return true; > > do we need that followup sync? Usermanual suggest sync; icbi(any address); > isync sequence. I don't know. The original implementation is here: https://github.com/linuxppc/linux/commit/0ce636700 Christophe
diff --git a/arch/powerpc/mm/mem.c b/arch/powerpc/mm/mem.c index ce6c81ce4362..19f807b87697 100644 --- a/arch/powerpc/mm/mem.c +++ b/arch/powerpc/mm/mem.c @@ -342,10 +342,9 @@ void free_initmem(void) /** * flush_coherent_icache() - if a CPU has a coherent icache, flush it - * @addr: The base address to use (can be any valid address, the whole cache will be flushed) * Return true if the cache was flushed, false otherwise */ -static inline bool flush_coherent_icache(unsigned long addr) +static inline bool flush_coherent_icache(void) { /* * For a snooping icache, we still need a dummy icbi to purge all the @@ -355,9 +354,7 @@ static inline bool flush_coherent_icache(unsigned long addr) */ if (cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) { mb(); /* sync */ - allow_read_from_user((const void __user *)addr, L1_CACHE_BYTES); - icbi((void *)addr); - prevent_read_from_user((const void __user *)addr, L1_CACHE_BYTES); + icbi((void *)PAGE_OFFSET); mb(); /* sync */ isync(); return true; @@ -397,7 +394,7 @@ static void invalidate_icache_range(unsigned long start, unsigned long stop) */ void flush_icache_range(unsigned long start, unsigned long stop) { - if (flush_coherent_icache(start)) + if (flush_coherent_icache()) return; clean_dcache_range(start, stop); @@ -509,7 +506,7 @@ void flush_dcache_icache_page(struct page *page) } else { unsigned long addr = page_to_pfn(page) << PAGE_SHIFT; - if (flush_coherent_icache(addr)) + if (flush_coherent_icache()) return; flush_dcache_icache_phys(addr); } @@ -528,7 +525,7 @@ static void __flush_dcache_icache(void *p) { unsigned long addr = (unsigned long)p; - if (flush_coherent_icache(addr)) + if (flush_coherent_icache()) return; clean_dcache_range(addr, addr + PAGE_SIZE);
flush_coherent_icache() can use any valid address as mentionned by the comment. Use PAGE_OFFSET as base address. This allows removing the user access stuff. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> --- arch/powerpc/mm/mem.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-)