@@ -105,28 +105,31 @@ extern s32 patch__flush_hash_B;
#include <asm/reg.h>
#include <asm/task_size_32.h>
-#define UPDATE_TWO_USER_SEGMENTS(n) do { \
+#define UPDATE_USER_SEGMENT(n, val) do { \
if (TASK_SIZE > ((n) << 28)) \
- mtsr(val1, (n) << 28); \
- if (TASK_SIZE > (((n) + 1) << 28)) \
- mtsr(val2, ((n) + 1) << 28); \
- val1 = (val1 + 0x222) & 0xf0ffffff; \
- val2 = (val2 + 0x222) & 0xf0ffffff; \
+ mtsr(val + (n) * 0x111, (n) << 28); \
} while (0)
static __always_inline void update_user_segments(u32 val)
{
- int val1 = val;
- int val2 = (val + 0x111) & 0xf0ffffff;
-
- UPDATE_TWO_USER_SEGMENTS(0);
- UPDATE_TWO_USER_SEGMENTS(2);
- UPDATE_TWO_USER_SEGMENTS(4);
- UPDATE_TWO_USER_SEGMENTS(6);
- UPDATE_TWO_USER_SEGMENTS(8);
- UPDATE_TWO_USER_SEGMENTS(10);
- UPDATE_TWO_USER_SEGMENTS(12);
- UPDATE_TWO_USER_SEGMENTS(14);
+ val &= 0xf0ffffff;
+
+ UPDATE_USER_SEGMENT(0, val);
+ UPDATE_USER_SEGMENT(1, val);
+ UPDATE_USER_SEGMENT(2, val);
+ UPDATE_USER_SEGMENT(3, val);
+ UPDATE_USER_SEGMENT(4, val);
+ UPDATE_USER_SEGMENT(5, val);
+ UPDATE_USER_SEGMENT(6, val);
+ UPDATE_USER_SEGMENT(7, val);
+ UPDATE_USER_SEGMENT(8, val);
+ UPDATE_USER_SEGMENT(9, val);
+ UPDATE_USER_SEGMENT(10, val);
+ UPDATE_USER_SEGMENT(11, val);
+ UPDATE_USER_SEGMENT(12, val);
+ UPDATE_USER_SEGMENT(13, val);
+ UPDATE_USER_SEGMENT(14, val);
+ UPDATE_USER_SEGMENT(15, val);
}
#endif /* !__ASSEMBLY__ */
segment register has VSID on bits 8-31. Bits 4-7 are reserved, there is no requirement to set them to 0. VSIDs are calculated from VSID of SR0 by adding 0x111. Even with highest possible VSID which would be 0xFFFFF0, adding 16 times 0x111 results in 0x1001100. So, the reserved bits are never overflowed, no need to clear the reserved bits after each calculation. Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> --- arch/powerpc/include/asm/book3s/32/mmu-hash.h | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-)